xr XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT MARCH 2005 REV. 1.0.1 Additional features include RLOS, a 16-bit LCV GENERAL DESCRIPTION counter for each channel, AIS, QRSS generation/ The XRT83SL314 is a fully integrated 14-channel detection, Network Loop Code generation/detection, short-haul line interface unit (LIU) that operates from TAOS, DMO, and diagnostic loopback modes. a single 3.3V power supply. Using internal APPLICATIONS termination, the LIU provides one bill of materials to operate in T1, E1, or J1 mode independently on a per T1 Digital Cross Connects (DSX-1) channel basis with minimum external components. ISDN Primary Rate Interface The LIU features are programmed through a standard microprocessor interface. EXARs LIU has patented CSU/DSU E1/T1/J1 Interface high impedance circuits that allow the transmitter T1/E1/J1 LAN/WAN Routers outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is Public Switching Systems and PBX Interfaces powered off. Key design features within the LIU T1/E1/J1 Multiplexer and Channel Banks optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without Integrated Multi-Service Access Platforms (IMAPs) using relays. Integrated Access Devices (IADs) The on-chip clock synthesizer generates T1/E1/J1 clock rates from a selectable external clock frequency Inverse Multiplexing for ATM (IMA) and has five output clock references that can be used Wireless Base Stations for external timing (8kHz, 1.544Mhz, 2.048Mhz, nxT1/J1, nxE1). FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL314 1 of 14 Channels NLCD Driver Generation Monitor TTIP Tx Pulse TCLK HDB3/B8ZS Tx Jitter Timing Line TPOS Shaper & Encoder Attenuator Control Driver TNEG Pattern Gen TRING Remote Digital Analog QRSS Loopback Loopback Loopback Generation & Detection RTIP Peak RCLK HDB3/B8ZS Rx Jitter Clock & Data Rx RPOS Detector Decoder Attenuator Recovery Equalizer RNEG & Slicer RRING Rx Equalizer Control NLCD AIS & LOS Detection Detector DMO RLOS 8kHzOUT ICT Test MCLKE1out Programmable Master TEST MCLKT1out Microprocessor Clock Synthesizer MCLKE1Nout Interface MCLKT1Nout RxON TxON RxTSEL Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com INT RDY TA CS ALE RD WE WR R/W uPCLK uPTS2 uPTS1 uPTS0 ADDR 10:0 DATA 7:0 Reset CS 5:1 MCLKinXRT83SL314 xr REV. 1.0.1 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT FEATURES Receiver line attenuation indication output in 1dB steps. Fully integrated 14-Channel short haul transceivers Loss of signal (RLOS) according to ITU-T G.775/ for T1/J1 (1.544MHz) and E1 (2.048MHz) applications. ETS300233 (E1) and ANSI T1.403 (T1/J1). T1/E1/J1 short haul and clock rate are per port Programmable receive slicer threshold (45%, 50%, selectable through software without changing 55%, or 68%) for improved receiver interference components. immunity. Internal Impedance matching on both receive and Programmable data stream muting upon RLOS transmit for 75 (E1), 100 (T1), 110 (J1), and detection. 120 (E1) applications are per port selectable On-Chip HDB3/B8ZS encoder/decoder with an through software without changing components. internal 16-bit LCV counter for each channel. Power down on a per channel basis with On-Chip digital clock recovery circuit for high input independent receive and transmit selection. jitter tolerance. Five pre-programmed transmit pulse settings for T1 QRSS pattern generator and detection for testing short haul applications. and monitoring. Arbitrary Pulse Generators for both T1 and E1 Error and bipolar violation insertion and detection. modes. Transmit all ones (TAOS) and in-band network loop On-Chip transmit short-circuit protection and up and loop down code generation. limiting protects line drivers from damage on a per Automatic loop code detection for remote loopback channel basis. activation. Independent Crystal-Less digital jitter attenuators Supports local analog, remote, digital, and dual (JA) with 32-Bit or 64-Bit FIFO for the receive and transmit paths loopback modes. On-Chip frequency multiplier generates T1 or E1 Low Power dissipation: 170mW per channel (50% master clocks from a variety of external clock density). sources (8, 16, 56, 64, 128, 256kHz and 1X, 2X, 250mW per channel maximum power dissipation 4X, 8X T1 or E1) (100% density). Driver failure monitor output (DMO) alerts of Single 3.3V supply operation (3V to 5V I/O possible system or external component problems. tolerant). Transmit outputs and receive inputs may beHig 304-Pin TBGA package impedance for protection or redundancy -40C to +85C Temperature Range applications on a per channel basis. Support for automatic protection switching. Supports gapped clocks for mapper/multiplexer applications. 1:1 and 1+1 protection without relays. Receive monitor mode handles 0 to 29dB resistive attenuation (flat loss) along with 0 to 6dB cable loss for both T1 and E1. PRODUCT ORDERING INFORMATION PRODUCT NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRT83SL314IB 304 Lead TBGA -40C to +85C 2