XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION 2013 REV. 2013 payload content of Receive LAPD Message frames GENERAL DESCRIPTION from the incoming T1/E1/J1 data stream and write the The XRT86VX38 is an eight-channel 1.544 Mbit/s or contents into the Receive HDLC buffers. Each framer 2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Short- also contains a Transmit and Overhead Data Input 3 port, which permits Data Link Terminal Equipment hual LIU integrated solution featuring R technology direct access to the outbound T1/E1/J1 frames. (Relayless, Reconfigurable, Redundancy) and BITS Likewise, a Receive Overhead output data port Timing element. The physical interface is optimized permits Data Link Terminal Equipment direct access with internal impedance, and with the patented pad to the Data Link bits of the inbound T1/E1/J1 frames. structure, the XRT86VX38 provides protection from power failures and hot swapping. The XRT86VX38 fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/ The XRT86VX38 contains an integrated DS1/E1/J1 E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/ framer and LIU which provide DS1/E1/J1 framing and E1.408-1990, AT&T TR 62411 (12-90) TR54016, and error accumulation in accordance with ANSI/ITU T ITU G-703, G.704, G706 and G.733, AT&T Pub. specifications. Each framer has its own framing 43801, and ETS 300 011, 300 233, JT G.703, JT synchronizer and transmit-receive slip buffers. The G.704, JT G706, I.431. Extensive test and diagnostic slip buffers can be independently enabled or disabled functions include Loop-backs, Boundary scan, as required and can be configured to frame to the Pseudo Random bit sequence (PRBS) test pattern common DS1/E1/J1 signal formats. generation, Performance Monitor, Bit Error Rate Each Framer block contains its own Transmit and (BER) meter, forced error insertion, and LAPD Receive T1/E1/J1 Framing function. There are 3 unchannelized data payload processing according to Transmit HDLC controllers per channel which ITU-T standard Q.921. encapsulate contents of the Transmit HDLC buffers Applications and Features (next page) into LAPD Message frames. There are 3 Receive HDLC controllers per channel which extract the FIGURE 1. XRT86VX38 EIGHT CHANNEL E1 (T1/E1/J1) FRAMER/LIU COMBO External Data Link Controller Local PCM Tx Overhead In Rx Overhead Out Highway XRT86VX38 1 of 8-channels 1:2 Turns Ratio TTIP 2-Frame Tx Serial Tx LIU Slip Buffer Tx Framer Data In Interface TRING Elastic Store Tx Serial Clock LLB LB 1:1 Turns Ratio RTIP 2-Frame Rx Serial Rx LIU Slip Buffer Rx Framer Data Out Interface RRING Elastic Store Rx Serial Clock LIU & PRBS Performance HDLC/LAPD Generator & Loopback RxLOS Monitor Controllers Control Analyser Line Side 8kHz sync OSC DMA Microprocessor Signaling & Interface JTAG Interface Alarms Back Plane 1.544-16.384 Mbit/s WR 3 4 ALE AS INT D 7:0 RD A 14:0 P System (Terminal) Side RDY DTACK Select TxON Intel/Motorola P Memory Configuration , Control & Status Monitor Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com ST-BUSXRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.4 APPLICATIONS High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems SONET/SDH terminal or Add/Drop multiplexers (ADMs) T1/E1/J1 add/drop multiplexers (MUX) Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 BITS Timing Digital Access Cross-connect System (DACs) Digital Cross-connect Systems (DCS) Frame Relay Switches and Access Devices (FRADS) ISDN Primary Rate Interfaces (PRA) PBXs and PCM channel bank T3 channelized access concentrators and M13 MUX Wireless base stations ATM equipment with integrated DS1 interfaces Multichannel DS1 Test Equipment T1/E1/J1 Performance Monitoring Voice over packet gateways Routers FEATURES Supports Section 13 - Synchronization Interface in ITU G.703 for both Transmit and Receive Paths Supports SSM Synchronous Messaging Generation (BOC for T1, National Bits for E1) on the Transmit Path Supports SSM Synchronous Messaging Extraction (BOC for T1, National Bits for E1) on the Receive Path Supports BITS timing generation on the Transmit Outputs Supports BITS timing extraction from NRZ data on the Analog Receive Path DS-0 Monitoring on both Transmit and Receive Time Slots Supports SSM Synchronization Messaging per ANSI T1.101-1999 and ITU G.704 Supports a Customized Section 13 - Synchronization Interface in G.703 at 1.544MHz Independent, full duplex DS1 Tx and Rx Framer/LIUs Each channel has full featured Long-haul/Short-haul LIU Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous back plane connections with jitter and wander attenuation Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus Programmable output clocks for Fractional T1/E1/J1 Supports Channel Associated Signaling (CAS) Supports Common Channel Signalling (CCS) Supports ISDN Primary Rate Interface (ISDN PRI) signaling 2