XRT94L43IB MaxLinear

XRT94L43 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER NOVEMBER 2006 REV. 1.0.2 FEATURES GENERAL DESCRIPTION Single Chip solution for 12 DS3/E3 to SONET/SDH The XRT94L43 is an SDH to PDH physical layer Mapping processor with integrated SONET OC-12 and 12 DS3/E3 framing controller. The XRT94L43 contains Generates and terminates SONET section, line and an integral SONET framer which provides framing path layers. and error accumulation in accordance with ANSI/ITU- Provides SONET frame scrambling and T specifications. For a multiple channel DS3/E3 descrambling. feature, each channel contains identical elements. The configuration of this device is through internal Differential Line Interfaces registers accessible via an 8-bit parallel, memory 8-bit microprocessor interface mapped, microprocessor interface. Requires +2.5 and +3.3V power supplies with +5V The SONET/SDH transmit and receive blocks are input tolerance used to transmit/receive an STS-12/STM-4 signals or compose and decompose 12, STS-1/DS3/E3 signals. -40C to +85C Operating Temperature Range The blocks operate at a peak internal clock speed of Available in a 516 Ball PBGA package 77 MHz and support 8-bit internal data paths. The transmit and receive blocks are compliant with both APPLICATIONS SONET and SDH standards. Network switches The XRT94L43 performs all SONET transport and path overhead processing for use in broadband data Concentrators transport applications. Frame Relay Switches SONET Customer Premises Multiplexers Network Access Equipment Test/Monitoring Equipment Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT94L43 REV. 1.0.2 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER FIGURE 1. BLOCK DIAGRAM OF THE XRT94L43 WHEN CONFIGURED IN SONET MODE TxTxTx TUTUTUGGG ---333 TxTxTx TUTUTUGGG ---333 TxTx AAUU --44 MMMaaapperpperpper /// TxTx AAUU --44 MMMaaapperpperpper /// MMaapperpper//VCVC --44 VCVCVC --- 333 PO PO POHHH TxTxTx VVVCCC ---333 VCVCVC --- 333 PO PO POHHH MMaapperpper//VCVC --44 TxTxTx VVVCCC ---333 TxTx SSTTMM --44 ProcProcProcessoressoressor TxTx SSTTMM --44 POHPOH POPOPOHHH ProcProcProcessoressoressor POHPOH POPOPOHHH SSOOH PH Prrocesocessorsor PPrrocesocessorsor BlBlBloooccckkk SSOOH PH Prrocesocessorsor ProcProcProcessessessororor PPrrocesocessorsor BlBlBloooccckkk ProcProcProcessoressoressor BlBloocckk BloBlocckk BlBloocckk BlBlBloooccckkk BloBlocckk BlBlBloooccckkk DSDSDS3/3/3/EEE333 DSDSDS3/3/3/EEE333 JiJiJitterttertter RRxx ST STMM -- 4 SOH4 SOH JiJiJitterttertter RRxx ST STMM -- 4 SOH4 SOH DSDSDS3/3/3/EEE333 DSDSDS3/3/3/EEE333 DSDSDS3/3/3/EEE333 AAAttenttenttenuuuaaatototorrr PPrrocesocessorsor DSDSDS3/3/3/EEE333 DSDSDS3/3/3/EEE333 DSDSDS3/3/3/EEE333 AAAttenttenttenuuuaaatototorrr PPrrocesocessorsor FraFraFraDSDSDSmmmererer3/3/3/EEE333 MMMaaappeppeppeDSDSDS3/3/3/rrr EEE333 FraFraFraDSDSDSmmmererer3/3/3/EEE333 DSDSDS3/3/3/EEE333 BlBlBloooccckkk BlBloocckk MMMaaappeppepperrr FrFrFramamamDSDSDSeee3/3/3/rrrEEE333 DSDSDS3/3/3/EEE333 BlBlBloooccckkk MMMaaappeppepperrr BlBloocckk BlBlBloooccckkk FramFramFramererer BlBlBlMMMoooaaacccppeppeppekkk rrr BlBlBlFrFrFroooamamamccckkk eeerrr MMMaaapperpperpper BlBlBloooccckkk BlBlBlFrFrFrooocccamamamkkk eeerrr BlBlBlMMMoooaaacccpperpperpperkkk BlBlBloooccckkk BlBlBloooccckkk BloBloBloccckkk BloBloBloccckkk BloBloBloccckkk BloBlocckk Block STSTMM --44 STSTMM --44 TeTelleeccoomm B Buuss TeTelleeccoomm B Buuss Rx ARx AUU --44 Rx TRx TRx TUUUGGG ---333 Rx ARx AUU --44 BlBloocckk Rx TRx TRx TUUUGGG ---333 BlBloocckk MMaapperpper//VCVC --44 MMMaaapperpperpper /// MMaapperpper//VCVC --44 MMMaaapperpperpper /// POHPOH VCVCVC --- 333 P P POOOHHH POHPOH VCVCVC --- 333 P P POOOHHH SSEERDERDESS PPrroceocessorssor ProcProcProcessoressoressor SSEERDERDESS PPrrocesocessorsor ProcProcProcessoressoressor BloBlocckk BloBlocckk BlBlBloooccckkk BloBlocckk BloBlocckk BlBloocckk (P(Pririmmaarryy)) (P(Pririmmaarryy)) AUAUGG 11 SESERRDDEESS ToTo A AUUGG 22 -- 44 SESERRDDESES BlBloocckk FrFromom A AUUG G 22 -- 44 BlBloocckk (A(APPSS)) ((AAPS)PS) CCllocock Syk Syntnthesihesizezer Br Bllockock MMiiccrroprocesoprocessor Isor Innterfacterfacee JTJTAAGG T Test est PortPort MMiiccrroprocesoprocessor Isor Innterfacterfacee CCllocock Syk Synthenthesisizerzer B Bllocockk JTJTAAGG T Test est PortPort 2