Revision 13 IGLOOe Low Power Flash FPGAs with Flash*Freeze Technology Bank-Selectable I/O VoltagesUp to 8 Banks per Chip Features and Benefits Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V/ 2.5V/1.8V/1.5V/1.2V, 3.3V PCI / 3.3V PCI-X, and Low Power LVCMOS 2.5 V / 5.0 V Input 1.2 V to 1.5 V Core Voltage Support for Low Power Differential I/O Standards: LVPECL, LVDS, B-LVDS, and Supports Single-Voltage System Operation M-LVDS Low-Power Active FPGA Operation Voltage-Referenced I/O Standards: GTL+ 2.5V/3.3V, GTL Flash*Freeze Technology Enables Ultra-Low Power 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Consumption while Maintaining FPGA Content Class I and II Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low- Wide Range Power Supply Voltage Support per JESD8-B, Power Flash*Freeze Mode Allowing I/Os to Operate from 2.7 V to 3.6 V High Capacity Wide Range Power Supply Voltage Support per JESD8-12, 600 k to 3 Million System Gates Allowing I/Os to Operate from 1.14 V to 1.575 V I/O Registers on Input, Output, and Enable Paths 108 to 504 kbits of True Dual-Port SRAM Up to 620 User I/Os Hot-Swappable and Cold-Sparing I/Os Programmable Output Slew Rate and Drive Strength Reprogrammable Flash Technology Programmable Input Delay 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Schmitt Trigger Option on Single-Ended Inputs Process Weak Pull-Up/-Down Instant On Level 0 Support IEEE 1149.1 (JTAG) Boundary Scan Test Single-Chip Solution Pin-Compatible Packages across the IGLOO e Family Retains Programmed Design when Powered Off Clock Conditioning Circuit (CCC) and PLL 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance Six CCC Blocks, Each with an Integrated PLL Configurable Phase Shift, Multiply/Divide, Delay Capabilities, In-System Programming (ISP) and Security and External Feedback ISP Using On-Chip 128-Bit Advanced Encryption Standard Wide Input Frequency Range (1.5 MHz up to 250 MHz) (AES) Decryption via JTAG (IEEE 1532compliant) Embedded Memory FlashLock Designed to Secure FPGA Contents 1 kbit of FlashROM User Nonvolatile Memory High-Performance Routing Hierarchy SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Segmented, Hierarchical Routing and Clock Structure Blocks (1, 2, 4, 9, and 18 organizations available) High-Performance, Low-Skew Global Network True Dual-Port SRAM (except 18) Architecture Supports Ultra-High Utilization ARM Processor Support in IGLOOe FPGAs Pro (Professional) I/O M1 IGLOOe DevicesCortex-M1 Soft Processor Available 700 Mbps DDR, LVDS-Capable I/Os with or without Debug 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Table 1 IGLOOe Product Family IGLOOe Devices AGLE600 AGLE3000 ARM-Enabled IGLOOe Devices M1AGLE3000 System Gates 600,000 3,000,000 VersaTiles (D-flip-flops) 13,824 75,264 Quiescent Current (typical) in Flash*Freeze Mode (W) 49 137 504 RAM kbits (1,024 bits) 108 112 4,608-Bit Blocks 24 1 FlashROM Kbits (1,024 bits) 1 Yes Secure (AES) ISP Yes 6 CCCs with Integrated PLLs 6 1 VersaNet Globals 18 18 8 I/O Banks 8 Maximum User I/Os 270 620 Package Pins FBGA FG256, FG484 FG484, FG896 Notes: 1. Refer to the Cortex-M1 Handbook for more information. 2. Six chip (main) and twelve quadrant global networks are available. 3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology datasheet. December 2012 I 2012 Microsemi CorporationIGLOOe Low Power Flash FPGAs 1 I/Os Per Package IGLOOe Devices AGLE600 AGLE3000 ARM-Enabled IGLOOe Devices M1AGLE3000 I/O Types Single-Ended Differential Single-Ended Differential 1 1 Package I/O I/O Pairs I/O I/O Pairs FG256 165 79 FG484 270 135 341 168 FG896 620 310 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOOe FPGA Fabric Users Guide to ensure compliance with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For AGLE3000 devices, the usage of certain I/O standards is limited as follows: SSTL3(I) and (II): up to 40 I/Os per north or south bank LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 4. FG256 and FG484 are footprint-compatible packages. 5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank (group of I/Os). 6. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user I/Os available is reduced by one. 7. indicates RoHS-compliant packages. Refer toIGLOOe Ordering Informatio on page III for the location of the in the part number. IGLOOe FPGAs Package Sizes Dimensions Package FG256 FG484 FG896 Length Width (mm mm) 17 17 23 23 31 31 Nominal Area (mm2) 289 529 961 Pitch (mm) 1 1 1 Height (mm) 1.6 2.23 2.23 IGLOOe Device Status IGLOOe Devices Status M1 IGLOOe Devices Status AGLE600 Production AGLE3000 Production M1AGLE3000 Production II Revision 13