v5.9v5.9 PLUS ProASIC Flash Family FPGAs High Performance Routing Hierarchy Features and Benefits Ultra-Fast Local and Long-Line Network High-Speed Very Long-Line Network High Capacity High-Performance, Low Skew, Splittable Global Network Commercial and Industrial 100% Routability and Utilization 75,000 to 1 Million System Gates I/O 27 K to 198 Kbits of Two-Port SRAM Schmitt-Trigger Option on Every Input 66 to 712 User I/Os 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate Military Bidirectional Global I/Os 300, 000 to 1 Million System Gates Compliance with PCI Specification Revision 2.2 72 K to 198 Kbits of Two Port SRAM Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant 158 to 712 User I/Os PLUS Pin-Compatible Packages across the ProASIC Family Reprogrammable Flash Technology Unique Clock Conditioning Circuitry 0.22 m 4 LM Flash-Based CMOS Process PLL with Flexible Phase, Multiply/Divide, and Delay Live At Power-Up (LAPU) Level 0 Support Capabilities Single-Chip Solution Internal and/or External Dynamic PLL Configuration No Configuration Device Required Two LVPECL Differential Pairs for Clock or Data Inputs Retains Programmed Design during Power-Down/Up Cycles Mil/Aero Devices Operate over Full Military Temperature Standard FPGA and ASIC Design Flow Range Flexibility with Choice of Industry-Standard Front-End Tools Efficient Design through Front-End Timing and Gate Performance Optimization 3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military temperature) ISP Support Two Integrated PLLs In-System Programming (ISP) via JTAG Port External System Performance up to 150 MHz SRAMs and FIFOs Secure Programming SmartGen Netlist Generation Ensures Optimal Usage of The Industrys Most Effective Security Key (FlashLock ) Embedded Memory Blocks 24 SRAM and FIFO Configurations with Synchronous and Low Power Asynchronous Operation up to 150 MHz (typical) Low Impedance Flash Switches Segmented Hierarchical Routing Structure Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells PLUS Table 1 ProASIC Product Profile 1 1 1 Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000 Maximum System Gates 75,000 150,000 300,000 450,000 600,000 750,000 1,000,000 Tiles (Registers) 3,072 6,144 8,192 12,288 21,504 32,768 56,320 Embedded RAM Bits (k=1,024 bits) 27 k 36k 72 k 108 k 126 k 144 k 198 k Embedded RAM Blocks (256x9) 12 16 32 48 56 64 88 LVPECL 222 2 2 2 2 PLL 222 2 2 2 2 Global Networks 4 4 4 4 4 4 4 Maximum Clocks 24 32 32 48 56 64 88 Maximum User I/Os 158 242 290 344 454 562 712 JTAG ISP Yes Yes Yes Yes Yes Yes Yes PCI Yes Yes Yes Yes Yes Yes Yes Package (by pin count) TQFP 100, 144 100 PQFP 208 208 208 208 208 208 208 PBGA 456 456 456 456 456 456 FBGA 144 144, 256 144, 256 144, 256, 484 256, 484, 676 676, 896 896, 1152 2 CQFP 208, 352 208, 352 208, 352 2 CCGA/LGA 624 624 Notes: 1. Available as Commercial/Industrial and Military/MIL-STD-883B devices. 2. These packages are available only for Military/MIL-STD-883B devices. December 2009 i 2009 Actel Corporation See the Actel website for the latest version of the datasheet.PLUS ProASIC Flash Family FPGAs Ordering Information APA1000 FG G 1152 I Application (Ambient Temperature Range) Blank = Commercial (0C to +70C) I = Industrial (40C to +85C) PP = Pre-production ES = Engineering Silicon (room temperature only) M = Military (55C to 125C) B = MIL-STD-883 Class B Package Lead Count Lead-free packaging Blank = Standard Packaging G = RoHS Compliant Packaging Package Type = TQ Thin Quad Flat Pack (0.5 mm pitch) = PQ Plastic Quad Flat Pack (0.5 mm pitch) = FG Fine Pitch Ball Grid Array (1.0 mm pitch) = BG Plastic Ball Grid Array (1.27 mm pitch) = CQ Ceramic Quad Flat Pack (1.05 mm pitch) = CG Ceramic Column Grid Array (1.27 mm pitch) = LG Land Grid Array (1.27 mm pitch) Speed Grade = Blank Standard Speed Part Number APA075 = 75,000 Equivalent System Gates APA150 = 150,000 Equivalent System Gates APA300 = 300,000 Equivalent System Gates APA450 = 450,000 Equivalent System Gates APA600 = 600,000 Equivalent System Gates APA750 = 750,000 Equivalent System Gates APA1000 = 1,000,000 Equivalent System Gates ii v5.9