AT17F16A FPGA Configuration Flash Memory DATASHEET Features Programmable 16,777, 216 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) 3.3V Output Capability 5.0V Tolerant I/O Pins Program Support using the Atmel ATDH2200E System, ATDH2225 ISP Cable, or Third-party Programmers In-System Programmable (ISP) via 2-wire Bus Simple Interface to SRAM FPGAs Compatible with Atmel AT40K and AT94K Devices, Altera FLEX , Excalibur , Stratix , Cyclone and APEX Devices Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Low-power CMOS FLASH Process Available in 8-pad LAP and 20-lead PLCC Packages Emulation of the Atmel AT24C Serial EEPROMs Low-power Standby Mode Single Device Capable of Holding Four Bitstream Files Allowing Simple System Reconfiguration Fast Serial Download Speeds up to 33MHz Endurance: 10,000 Write Cycles Typical Green (Pb/Halide-free/RoHS Compliant) Packages Description The Atmel AT17F16A In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory solution for FPGAs. The AT17F16A is packaged in the 8-pad LAP and 20-lead PLCC (Table 1). The AT17F16A uses a simple serial-access procedure to configure one or more FPGA devices. The AT17F16A can be programmed with industry-standard programmers, the Atmel ATDH2200E Programming Kit, or the Atmel ATDH2225 ISP Cable. Table 1. AT17F16A Series Packages Package AT17F16A 8-pad LAP Yes 20-lead PLCC Yes Atmel-3474F-CNFG-AT17F16A-Datasheet 0120151. Pin Configurations Table 1-1. Pin Descriptions Pin Description Three-state DATA output for FPGA Configuration. Open-collector bi-directional pin for (1) DATA configuration programming. Three-state Clock. Functions as an input when the Configurator is in programming mode (i.e. (1) DCLK SER EN is Low) and as an output during FPGA configuration. Enable Page Download Mode Input. When PAGE EN is high the configuration download address space is partitioned into four equal pages. This gives users the ability to easily store and retrieve (2) PAGE EN multiple configuration bitstreams from a single configuration device. This input works in conjunction with the PAGESEL inputs. PAGE EN must be remain low if paging is not desired. When SER EN is Low (ISP mode) this pin has no effect. Page Select Inputs. Used to determine which of the four memory pages are targeted during a serial (2) PAGESEL 1:0 configuration download. The address space for each of the pages is shown in Table 1-2. When SER EN is Low (ISP mode) these pins have no effect. Output Enable (Active High) and RESET (Active Low) when SER EN is High. A Low level on (1) RESET/OE RESET/OE resets both the address and bit counters. A High level (with nCS Low) enables the data output driver. Chip Enable Input (Active Low). A Low level (with OE High) allows DCLK to increment the address counter and enables the data output driver. A High level on nCS disables both the address and bit (1) nCS counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode (SER EN Low). GND Ground. A 0.2F decoupling capacitor between V and GND is recommended. CC Cascade Select Output (when SER EN is High). This output goes Low when the internal address counter has reached its maximum value. If the PAGE EN input is set High, the maximum value is the highest address in the selected partition. The PAGESEL 1:0 inputs are used to make the four partition selections. If the PAGE EN input is set Low, the device is not partitioned and the address nCASC maximum value is the highest address in the device (Table 1-2). In a daisy chain of the AT17FxxxA Series devices, the nCASC pin of one device must be connected to the nCS input of the next device in the chain. It will stay Low as long as nCS is Low and OE is High. It will then follow nCS until OE goes Low thereafter, nCASC will stay High until the entire EEPROM is read again. Device Selection Input, (when SER EN Low). The input is used to enable (or chip select) the (1) A2 device during programming (i.e., when SER EN is Low). Refer to the Atmel AT17FxxxA Programming Specification available at www.atmel.com for additional details. Open Collector Reset State Indicator. Driven Low during power-up reset, released when power-up READY is complete. (recommended 4.7k pull-up on this pin if used). Serial Enable Input. Must remain High during FPGA configuration operations. Bringing SER EN (1) SER EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER EN should be tied to V . CC V Device Power Supply. +3.3V (10%) CC Notes: 1. Internal 20K pull-up resistor 2. Internal 30K pull-up resistor 2 AT17F16A DATASHEET Atmel-3474F-CNFG-AT17F16A-Datasheet 012015