Features
Fast Read Access Time 70 ns
Automatic Page Write Operation
Internal Address and Data Latches for 64 Bytes
Internal Control Timer
Fast Write Cycle Times
Page Write Cycle Time: 3 ms or 10 ms Maximum
1 to 64-byte Page Write Operation
Low Power Dissipation
256K (32K x 8)
80 mA Active Current
3 mA Standby Current
High-speed
Hardware and Software Data Protection
DATA Polling for End of Write Detection
Parallel
High Reliability CMOS Technology
4 5
or 10 Cycles
Endurance: 10
EEPROM
Data Retention: 10 Years
Single 5V 10% Supply
CMOS and TTL Compatible Inputs and Outputs
AT28HC256
JEDEC Approved Byte-wide Pinout
Full Military and Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Option
1. Description
The AT28HC256 is a high-performance electrically erasable and programmable read-
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-
tured with Atmels advanced nonvolatile CMOS technology, the AT28HC256 offers
access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256
is deselected, the standby current is less than 5 mA.
The AT28HC256 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64
bytes of data are internally latched, freeing the addresses and data bus for other oper-
ations. Following the initiation of a write cycle, the device will automatically write the
latched data using an internal control timer. The end of a write cycle can be detected
by DATA Polling of I/O7. Once the end of a write cycle has been detected a new
access for a read or write can begin.
Atmels 28HC256 has additional features to ensure high quality and manufacturability.
The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra
64 bytes of EEPROM for device identification or tracking.
0007NPEEPR9/092. Pin Configurations
Pin Name Function
A0 - A14 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Dont Connect
2.3 32-pad LCC, 32-lead PLCC Top View
2.1 28-lead TSOP Top View
OE 1 28 A10
2
A11 27 CE
A6 5 29 A8
A9 3 26 I/O7
A5 6 28 A9
A8 4 25 I/O6
A4 7 27 A11
A13 5 24 I/O5
A3 8 26 NC
WE 6 23 I/O4
A2 9 25 OE
VCC 7 22 I/O3
A1 10 24 A10
A14 8 21 GND
A0 11 23 CE
A12 9
20 I/O2
NC 12 22 I/O7
A7 10 19 I/O1
I/O0 13 21 I/O6
A6 11 18 I/O0
A5 12 17 A0
A4 13 16 A1
A3 14 15 A2
Note: PLCC package pins 1 and 17 are Dont Connect.
2.4 28-lead Cerdip/Flatpack/SOIC
2.2 28-lead PGA Top View
Top View
A14 1 28 VCC
A12 2 27 WE
A7 3 26 A13
A6 4 25 A8
A5 5 24 A9
A4 6 23 A11
A3 7 22 OE
A2 8 21 A10
A1 9 20 CE
A0 10 19 I/O7
I/O0 11 18 I/O6
I/O1 12 17 I/O5
I/O2 13 16 I/O4
GND 14 15 I/O3
2
AT28HC256
0007NPEEPR9/09
I/O1 14 4 A7
I/O2 15 3 A12
GND 16 2 A14
DC 17 1 DC
I/O3 18 32 VCC
I/O4 19 31 WE
I/O5 20 30 A13