Features High-performance System Speeds > 100 MHz Flip-flop Toggle Rates > 250 MHz 1.2 ns/1.5 ns Input Delay 3.0 ns/6.0 ns Output Delay Up to 204 User I/Os Up to 6,400 Registers Cache Logic Design Complete/Partial In-System Reconfiguration No Loss of Data or Machine State Coprocessor Adaptive Hardware Low Voltage and Standard Voltage Operation Field 5.0(V = 4.75V to 5.25V) CC 3.3(V =3.0Vto3.6V) CC Programmable Automatic Component Generators Reusable Custom Hard Macro Functions Gate Arrays Very Low-power Consumption Standby Current of 500 A/ 200 A Typical Operating Current of 15 to 170 mA Programmable Clock Options AT6000(LV) Independently Controlled Column Clocks Independently Controlled Column Resets Clock Skew Less Than 1 ns Across Chip Series Independently Configurable I/O (PCI Compatible) TTL/CMOS Input Thresholds Open Collector/Tristate Outputs Programmable Slew-rate Control I/O Drive of 16 mA (combinable to 64 mA) Description AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for use as reconfigurable coprocessors and implementing compute-intensive logic. Supporting system speeds greater than 100 MHz and using a typical operating current of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive designs. These FPGAs are designed to implement Cache Logic, which provides the user with the ability to implement adaptive hardware and perform hardware acceleration. The patented AT6000 Series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is surrounded by programmable I/O. Obsolete: Not (continued) AT6000 Series Field Programmable Gate Arrays Recommended for Device AT6002* AT6003* AT6005 AT6010 New Design Usable Gates 6,000 9,000 15,000 30,000 AT6000LV Series Cells 1,024 1,600 3,136 6,400 AT6002* Registers (maximum) 1,024 1,600 3,136 6,400 AT6003* I/O (maximum) 96 120 108 204 Typ. Operating Current (mA) 15-30 25-45 40-80 85 - 170 Cell Rows x Columns 32x32 40x40 56x56 80x80 Atmel-0264G-FPGA-AT6000(LV)-Datasheet 042015Devices range in size from 4,000 to 30,000 usable gates, The Symmetrical Array and 1024 to 6400 registers. Pin locations are consistent At the heart of the Atmel architecture is a symmetrical array throughout the AT6000 Series for easy design migration. of identical cells (Figure 1). The array is continuous and High-I/O versions are available for the lower gate count completely uninterrupted from one edge to the other, devices. except for bus repeaters spaced every eight cells AT6000 Series FPGAs utilize a reliable 0.6 m single-poly, (Figure 2). double-metal CMOS process and are 100% factory-tested. In addition to logic and storage, cells can also be used as Atmel s PC- and workstation-based Integrated Develop- wires to connect functions together over short distances ment System is used to create AT6000 Series designs. and are useful for routing in tight spaces. Multiple design entry methods are supported. The Atmel architecture was developed to provide the high- The Busing Network est levels of performance, functional density and design There are two kinds of buses: local and express (see flexibility in an FPGA. The cells in the Atmel array are Figures 2 and 3). small, very efficient and contain the most important and Local buses are the link between the array of cells and the most commonly used logic and wiring functions. The cells busing network. There are two local buses North-South 1 small size leads to arrays with large numbers of cells, and 2 (NS1 and NS2) for every column of cells, and two greatly multiplying the functionality in each cell. A simple, local buses East-West 1 and 2 (EW1 and EW2) for high-speed busing network provides fast, efficient commu- everyrowofcells.Inasector(an8x8arrayofcells nication over medium and long distances. enclosed by repeaters) each local bus is connected to every cell in its column or row, thus providing every cell in the array with read/write access to two North-South and two East-West buses. Figure 1. Symmetrical Array Surrounded by I/O 2 AT6000(LV) Series Atmel-0264G-FPGA-AT6000(LV)-Datasheet 042015