Revision 18 Axcelerator Family FPGAs Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, Leading-Edge Performance SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 350+ MHz System Performance Registered I/Os 500+ MHz Internal Performance Hot-Swap Compliant I/Os (except PCI) High-Performance Embedded FIFOs Programmable Slew Rate and Drive Strength on Outputs 700 Mb/s LVDS Capable I/Os Programmable Delay and Weak Pull-Up/Pull-Down Circuits Specifications on Inputs Embedded Memory: Up to 2 Million Equivalent System Gates Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4, x9, x18, Up to 684 I/Os x36 Organizations Available) Up to 10,752 Dedicated Flip-Flops Independent, Width-Configurable Read and Write Ports Up to 295 kbits Embedded SRAM/FIFO Programmable Embedded FIFO Control Logic Manufactured on Advanced 0.15 m CMOS Antifuse Process Segmentable Clock Resources Technology, 7 Layers of Metal Embedded Phase-Locked Loop: Features 14-200 MHz Input Range Single-Chip, Nonvolatile Solution Frequency Synthesis Capabilities up to 1 GHz Up to 100% Resource Utilization with 100% Pin Locking Deterministic, User-Controllable Timing 1.5 V Core Voltage for Low Power Unique In-System Diagnostic and Debug Capability with Footprint Compatible Packaging Microsemi Silicon Explorer II Flexible, Multi-Standard I/Os: Boundary-Scan Testing Compliant with IEEE Standard 1149.1 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation (JTAG) Bank-Selectable I/Os 8 Banks per Chip FuseLock Programming Technology Protects Against Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V PCI, Reverse Engineering and Design Theft and 3.3 V PCI-X Differential I/O Standards: LVPECL and LVDS Table 1 Axcelerator Family Product Profile Device AX125 AX250 AX500 AX1000 AX2000 Capacity (in Equivalent System Gates) 125,000 250,000 500,000 1,000,000 2,000,000 Typical Gates 82,000 154,000 286,000 612,000 1,060,000 Modules Register (R-cells) 672 1,408 2,688 6,048 10,752 Combinatorial (C-cells) 1,344 2,816 5,376 12,096 21,504 Maximum Flip-Flops 1,344 2,816 5,376 12,096 21,504 Embedded RAM/FIFO Number of Core RAM Blocks 4 12 16 36 64 Total Bits of Core RAM 18,432 55,296 73,728 165,888 294,912 Clocks (Segmentable) Hardwired 4 4 4 4 4 Routed 4 4 4 4 4 PLLs 88 88 8 I/Os I/O Banks 8 8 8 8 8 Maximum User I/Os 168 248 336 516 684 Maximum LVDS Channels 84 124 168 258 342 Total I/O Registers 504 744 1,008 1,548 2,052 Package PQ 208 208 BG 729 FG 256, 324 256, 484 484, 676 484, 676, 896 896, 1152 CQ 208, 352 208, 352 352 256, 352 CG 624 624 March 2012 i 2012 Microsemi CorporationAxcelerator Family FPGAs Ordering Information AX1000 1 FG G 896 I Application Blank =Commercial (0 to +70 C) PP = Pre-Production I = Industrial (-40 to +85 C) M = Military (-55 to +125 C) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging Package Type = BG Ball Grid Array (1.27mm pitch) = FG Fine Ball Grid Array (1.0mm pitch) PQ= Plastic Quad Flat Pack (0.5mm pitch) = CQ Ceramic Quad Flat Pack (0.5mm pitch) = CG Ceramic Column Grid Array Speed Grade Blank = Standard Speed = Approximately 15% Faster than Standard 1 = 2 Approximately 25% Faster than Standard Part Number AX125 = 125,000 Equivalent System Gates AX250 = 250,000 Equivalent System Gates AX500 = 500,000 Equivalent System Gates AX1000 = 1,000,000 Equivalent System Gates AX2000 = 2,000,000 Equivalent System Gates Device Resources User I/Os (Including Clock Buffers) Package AX125 AX250 AX500 AX1000 AX2000 PQ208 115 115 CQ208 115 115 CQ256 136 FG256 138 138 FG324 168 CQ352 198 198 198 198 FG484 248 317 317 CG624 418 418 FG676 336 418 BG729 516 FG896 516 586 FG1152 684 Note: The FG256, FG324, and FG484 are footprint compatible with one another. The FG676, FG896, and FG1152 are also footprint compatible with one another. ii Revision 18