dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, ADC and Comparators Operating Conditions Advanced Analog Features (Continued) ADC module: 3.0V to 3.6V, -40C to +125C, DC to 40 MIPS - 10-bit resolution with Successive Approximation Register (SAR) converter (2 Msps) and three Core: 16-Bit dsPIC33F CPU Sample-and-Hold (S&H) circuits Code Efficient (C and Assembly) Architecture - Up to 8 input channels grouped into four conversion Two 40-Bit Wide Accumulators pairs, plus two inputs for monitoring voltage references Single-Cycle (MAC/MPY) with Dual Data Fetch - Flexible and independent ADC trigger sources Single-Cycle Mixed-Sign MUL plus Hardware Divide - Dedicated Result register for each 32-Bit Multiply Support analog channel Clock Management Timers/Output Compare/Input Capture Two 16-Bit General Purpose Timers/Counters 2% Internal Oscillator Input Capture module Programmable PLLs and Oscillator Clock Sources Output Compare module Fail-Safe Clock Monitor (FSCM) Peripheral Pin Select (PPS) to allow Function Remap Independent Watchdog Timer (WDT) Fast Wake-up and Start-up Communication Interfaces Power Management UART module (10 Mbps): - With support for LIN/J2602 protocols and IrDA Low-Power Management modes (Sleep, Idle, Doze) 4-Wire SPI module Integrated Power-on Reset and Brown-out Reset 2 I C module (up to 1 Mbaud) with SMBus Support 2.0 mA/MHz Dynamic Current (typical) PPS to allow Function Remap 135 A IPD Current (typical) Input/Output High-Speed PWM Constant Current Source: Up to Three PWM Pairs with Independent Timing - Constant current generator (10 A nominal) Dead Time for Rising and Falling Edges Sink/Source 18 mA on 8 Pins and 6 mA on 13 Pins 1.04 ns PWM Resolution for Dead Time, Duty Cycle, 5V Tolerant Pins Phase and Frequency Selectable Open-Drain and Pull-ups PWM Support for: External Interrupts on 16 I/O Pins - DC/DC, AC/DC, Inverters, PFC and Lighting Programmable Fault Inputs Qualification and Class B Support Flexible Trigger Configurations for ADC Conversions AEC-Q100 REVG (Grade 1, -40C to +125C) Planned Class B Safety Library, IEC 60730 Advanced Analog Features Debugger Development Support Two High-Speed Comparators with Direct Connection to the PWM module: In-Circuit and In-Application Programming - Buffered/amplified output drive Two Breakpoints - Independent 10-bit DAC for each comparator IEEE 1149.2 Compatible (JTAG) Boundary Scan - Rail-to-rail comparator operation Trace and Run-Time Watch - DACOUT amplifier (1x, 1.8x) - Selectable hysteresis - Programmable output polarity - Interrupt generation capability 2011-2012 Microchip Technology Inc. DS75018C-page 1dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT FAMILIES The device names, pin counts, memory sizes and periph- eral availability of each device are listed in Table 1. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT FAMILIES Remappable Peripherals ADC Device PDIP, 18 SOIC dsPIC33FJ06GS001 6 256 8 2 0 0 0 0 2x2 2 3 00011 2 6 13 20 SSOP PDIP, 18 SOIC dsPIC33FJ06GS101A 6 256 8 2 0 1 1 1 2x2 0 3 00111 3 6 13 20 SSOP SPDIP, SOIC, 28 SSOP, dsPIC33FJ06GS102A 6 256 16 2 0 1 1 1 2x2 0 3 00111 3 6 21 QFN-S 36 VTLA SPDIP, SOIC, 28 SSOP, dsPIC33FJ06GS202A 6 1K 16 2 1 1 1 1 2x2 2 3 10111 3 6 21 QFN-S 36 VTLA SPDIP, SOIC, 28 SSOP, dsPIC33FJ09GS302 9 1K 16 2 1 1 1 1 3x2 2 3 11111 3 8 21 QFN-S 36 VTLA Note 1: INT0 is not remappable. 2: The PWM4 pair is remappable and only available on dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302 devices. DS75018C-page 2 2011-2012 Microchip Technology Inc. Pins Program Flash Memory (Kbytes) RAM (Bytes) Remappable Pins 16-Bit Timer Input Capture Output Compare UART SPI (2) PWM Analog Comparator (1) External Interrupts DAC Output Constant Current Source Reference Clock 2 I C SARs Sample-and-Hold (S&H) Circuit Analog-to-Digital Inputs I/O Pins Packages