HV7224PG-G

Supertex inc. HV7224 40-Channel Symmetric Row Driver Features General Description HVCMOS technology The HV7224 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. It is especially suitable for use Symmetric row drive (reduces latent imaging in ACTFEL displays) as a symmetric row driver in AC thin-film electroluminescent Output voltage up to +240V (ACTFEL) displays. Low power level shifting When the data reset pin (DR A/DR B) is at logic high, it will reset Source/sink current minimum 70mA IO IO all the outputs of the internal shift register to zero. At the same Shift register speed 3.0MHz time, the output of the shift register will start shifting a logic high Pin-programmable shift direction (DIR, SHIFT) from the least significant bit to the most significant bit. The DR A/ IO DR B can be triggered at any time. The DIR and SHIFT pins IO control the direction of data shift through the device. When DIR is at logic high, DR A is the input and DR B is the output. When DIR IO IO is grounded, DR B is the input and the DR A is the output. See IO IO the Output Sequence Operation Table for output sequence. The POL and OE pins perform the polarity select and output enable function respectively. Data is loaded on the low to high transition of the clock. A logic high will cause the output to swing to VPP if POL is high, or to GND if POL is low. All outputs will be in High-Z state if OE is at logic high. Data output buffers are provided for cascading devices. Functional Block Diagram VPP OE POL VDD P Level HV 1 Translator OUT DR A N IO SHIFT P CLK Level HV 2 OUT Translator S/R DIR N P DR B IO Level HV 40 OUT Translator N GND Doc. DSFP-HV7224 Supertex inc. C072413 www.supertex.comHV7224 Pin Configuration Ordering Information 64 Part Number Package Packing HV7224PG-G 64-Lead PQFP 66/Tray -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value 1 Supply voltage, V -0.5V to +7.0V DD 64-Lead PQFP (3-sided) (top view) Supply voltage , V -0.5V to +260V PP Logic input levels -0.5V to V + 0.5V DD Product Marking 1 Continuous total power dissipation 1200mW L = Lot Number Top Marking YY = Year Sealed Operating temperature range -40C to +85C HV7224PG WW = Week Sealed LLLLLLLLLL Storage temperature range -65C to +150C YYWW C = Country of Origin CCCCCCCC AAA A = Assembler ID Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not = Green Packaging implied. Continuous operation of the device at the absolute rating level Package may or may not include the following marks: Si or may affect device reliability. All voltages are referenced to device ground. 64-Lead PQFP (3-sided) Note: 1. For operation above 25C ambient derate linearly to maximum operating temperature at 20mW/C. Typical Thermal Resistance Package ja O 44-Lead PLCC 37 C/W Recommended Operating Conditions Sym Parameter Min Max Units V Logic supply voltage 4.5 5.5 V DD 1 V High voltage supply 0 240 V PP V High-level input voltage 0.7 V V V IH DD DD V Low-level input voltage 0 0.2V V IL DD f Clock frequency - 3.0 MHz CLK T Operating free-air temperature -40 +85 C A I High voltage output current - 70 mA O I Allowable pulsed current through output diode - 300 mA OD Note: 1. Output will not switch at V = 0V. PP Power-up sequence should be the following: 1. Connect ground. 2. Apply V . DD 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply V . PP The V should not drop below V or float during operation. PP DD Power-down sequence should be the reverse of the above. Doc. DSFP-HV7224 Supertex inc. C072413 2 www.supertex.com