KSZ8463FMLI

KSZ8463ML/RL/FML/FRL IEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII or RMII Port 2 and Source Address Filtering for Imple- Features menting Ring Topologies Management Capabilities MAC Filtering Function to Filter or Forward The KSZ8463ML/RL/FML/FRL Includes All the Unknown Unicast Packets Functions of a 10/100BASE-T/TX/FX Switch Sys- Port 1 and Port 2 MACs Programmable as Either tem that Combines a Switch Engine, Frame Buffer E2E or P2P Transparent Clock (TC) Ports for Management, Address Look-Up Table, Queue 1588 Support Management, MIB Counters, Media Access Con- Port 3 MAC Programmable as Slave or Master of trollers (MAC) and PHY Transceivers Ordinary Clock (OC) Port for 1588 Support Non-Blocking Store-and-Forward Switch Fabric Microchip LinkMD Cable Diagnostic Capabilities Ensures Fast Packet Delivery by Utilizing 1024 for Determining Cable Opens, Shorts, and Length Entry Forwarding Table Advanced Switch Capabilities Port Mirroring/Monitoring/Sniffing: Ingress and/or Egress Traffic to any Port Non-Blocking Store-and-Forward Switch Fabric Ensures Fast Packet Delivery by Utilizing 1024 MIB Counters for Fully Compliant Statistics Gath- Entry Forwarding Table ering: 34 Counters per Port IEEE 802.1Q VLAN for Up to 16 Groups with Full Loopback Modes for Remote Failure Diagnostics Range of VLAN IDs Rapid Spanning Tree Protocol Support (RSTP) for IEEE 802.1p/Q Tag Insertion or Removal on a per Topology Management and Ring/Linear Recovery Port Basis (Egress) and Support Double-Tagging Bypass Mode Ensures Continuity Even When a VLAN ID Tag/Untag Options on per Port Basis Host is Disabled or Fails Fully Compliant with IEEE 802.3/802.3u Stan- Robust PHY Ports dards Two Integrated IEEE 802.3/802.3u-Compliant IEEE 802.3x Full-Duplex with Force-Mode Option Ethernet Transceivers Supporting 10BASE-T and and Half-Duplex Backpressure Collision Flow 100BASE-TX Control Copper and 100BASE-FX Fiber Mode Support in IEEE 802.1w Rapid Spanning Tree Protocol Sup- the KSZ8463FML and KSZ8463FRL port Copper Mode Support in the KSZ8463ML and IGMP v1/v2/v3 Snooping for Multicast Packet Fil- KSZ8463RL tering On-Chip Termination Resistors and Internal Bias- QoS/CoS Packets Prioritization Support: 802.1p, ing for Differential Pairs to Reduce Power DiffServ-Based and Re-Mapping of 802.1p Prior- HP Auto MDI/MDI-X Crossover Support Elimi- ity Field per Port Basis on Four Priority Levels nates the Need to Differentiate Between Straight IPv4/IPv6 QoS Support or Crossover Cables in Applications IPv6 Multicast Listener Discovery (MLD) Snoop- MAC Ports ing Support Three Internal Media Access Control (MAC) Units Programmable Rate Limiting at the Ingress and MII or RMII Interface Support on MAC Port 3 Egress Ports Broadcast Storm Protection 2Kbyte Jumbo Packet Support Bypass Mode to Sustain the Switch Function Tail Tagging Mode (One byte Added before FCS) between Port 1 and Port 2 when CPU (Port 3) Support at Port 3 to Inform The Processor Which Goes into Sleep Mode Ingress Port Receives the Packet and its Priority 1K Entry Forwarding Table with 32K Frame Buffer Supports Reduced Media Independent Interface (RMII) with 50 MHz Reference Clock Input or Out- Four Priority Queues with Dynamic Packet Map- put ping for IEEE 802.1p, IPv4 TOS (DIFFSERV), IPv6 Traffic Class, etc. Supports Media Independent Interface (MII) in Either PHY Mode or MAC Mode on Port 3 Programmable MAC Addresses for Port 1 and 2018 Microchip Technology Inc. DS00002642A-page 1KSZ8463ML/RL/FML/FRL Comprehensive Configuration Registers Access Energy Detect Power-Down (EDPD), which Dis- ables the PHY Transceiver when Cables are High-Speed SPI (4-Wire, Up to 50 MHz) Interface Removed to Access All Internal Registers Dynamic Clock Tree Control to Reduce Clocking MII Management (MIIM, MDC/MDIO 2-Wire) in Areas Not in Use Interface to Access All PHY Registers per Clause Power Consumption Less than 0.5W 22.2.4.5 of the IEEE 802.3 Specification I/O Pin Strapping Facility to Set Certain Register Additional Features Bits from I/O Pins at Reset Time Single 25 MHz 50 ppm Reference Clock Control Registers Configurable On-the-Fly Requirement for MII Mode IEEE 1588v2 PTP and Clock Synchronization Selectable 25 MHz or 50 MHz Inputs for RMII Mode Fully Compliant with the IEEE 1588v2 Precision Comprehensive Programmable Two LED Indica- Time Protocol tors Support for Link, Activity, Full-/Half-Duplex One-Step or Two-Step Transparent Clock (TC) and 10/100 Speed Timing Corrections LED Pins Directly Controllable E2E (End-to-End) or P2P (Peer-to-Peer) Trans- Industrial Temperature Range: 40C to +85C parent Clock (TC) 64-Pin (10 mm x 10 mm) Lead Free (ROHS) Grandmaster, Master, Slave, Ordinary Clock (OC) LQFP Package Support Applications IEEE1588v2 PTP Multicast and Unicast Frame Support Industrial Ethernet Applications that Employ IEEE Transports of PTP Over IPv4/IPv6 UDP and IEEE 802.3-Compliant MACs. (Ethernet/IP, Profinet, 802.3 Ethernet MODBUS TCP, etc) Delay Request-Response and Peer Delay Mech- Real-Time Ethernet Networks Requiring Sub- anism Microsecond Synchronization over Standard Ingress/Egress Packet time stamp Capture/ Ethernet Recording and Checksum Update IEC 61850 Networks Supporting Power Substa- Correction Field Update with Residence Time and tion Automation Link Delay Networked Measurement and Control Systems IEEE1588v2 PTP Packet Filtering Unit to Reduce Industrial Automation and Motion Control Sys- Host Processor Overhead tems A 64-bit Adjustable System Precision Clock Test and Measurement Equipment Twelve Trigger Output Units and Twelve time stamp Input Units Available for Flexible IEEE1588v2 Control of Twelve Programmable GPIO 11:0 Pins Synchronized to the Precision Time Clock GPIO Pin Usage for 1 PPS Generation, Fre- quency Generator, Control Bit Streams, Event Monitoring, Precision Pulse Generation, Complex Waveform Generation Power and Power Management Single 3.3V Power Supply with Optional VDD I/O for 1.8V, 2.5V, or 3.3V Integrated Low Voltage (~1.3V) Low-Noise Regu- lator (LDO) Output for Digital and Analog Core Power Supports IEEE P802.3az Energy Efficient Ethernet (EEE) to Reduce Power Consumption in Transceivers in LPI State Full-Chip Hardware or Software Power-Down (All Registers Value are Not Saved and Strap-In Value will Re-Strap After Release the Power-Down) DS00002642A-page 2 2018 Microchip Technology Inc.