KSZ8567S 7-Port 10/100 Ethernet AVB Switch with SGMII and RGMII/MII/RMII Interfaces Five Integrated PHY Ports Highlights - 100BASE-TX/10BASE-T/Te IEEE 802.3 One port with 10/100/1000 Ethernet MAC - Fast Link-up option significantly reduces link-up time and SGMII interface - Auto-negotiation and Auto-MDI/MDI-X support One port with 10/100/1000 Ethernet MAC - Energy-Efficient Ethernet (EEE) support with low- and configurable RGMII/MII/RMII interface power idle mode and clock stoppage EtherSynch with full support for IEEE 1588v2 - On-chip termination resistors and internal biasing for differential pairs to reduce power Precision Time Protocol (PTP) - LinkMD cable diagnostic capabilities for determining IEEE 802.1AS/Qav Audio Video Bridging (AVB) cable opens, shorts, and length IEEE 802.3az Energy Efficient Ethernet (EEE) Advanced Switch Capabilities IEEE 802.1X access control support - IEEE 802.1Q VLAN support for 128 active VLAN Five ports with integrated 10/100BASE-T PHY trans- groups and the full range of 4096 VLAN IDs ceivers with optional Quiet-WIRE EMC filtering - IEEE 802.1p/Q tag insertion/removal on per port basis Non-blocking wire-speed Ethernet switching fabric - VLAN ID on per port or VLAN basis Full-featured forwarding and filtering control, includ- - IEEE 802.3x full-duplex flow control and half-duplex ing Access Control List (ACL) filtering back pressure collision control Full VLAN and QoS support - IEEE 802.1X access control (Port and MAC address) EtherGreen power management features, - IGMP v1/v2/v3 snooping for multicast packet filtering including low power standby - IPv6 multicast listener discovery (MLD) snooping 2 - IPv4/IPv6 QoS support, QoS/CoS packet prioritization Flexible management interface options: SPI, I C, - 802.1p QoS packet classification with 4 priority queues MIIM, and in-band management via any port - Programmable rate limiting at ingress/egress ports Extended temperature range support IEEE 1588v2 PTP and Clock Synchronization 128-pin TQFP-EP (14 x 14mm) RoHS compliant pkg - Transparent Clock (TC) with auto correction update - Master and slave Ordinary Clock (OC) support Target Applications - End-to-end (E2E) or peer-to-peer (P2P) Industrial Ethernet (Profinet, MODBUS, Ethernet/IP) - PTP multicast and unicast message support - PTP message transport over IPv4/v6 and IEEE 802.3 Real-time Ethernet networks - IEEE 1588v2 PTP packet filtering IEC 61850 networks w/ power substation automation - Synchronous Ethernet support via recovered clock Industrial control/automation switches Audio Video Bridging (AVB) Networked measurement and control systems - Compliant with IEEE 802.1BA/AS/Qat/Qav standards Test and measurement equipment - Priority queuing, Low latency cut-through mode - gPTP time synchronization, credit-based traffic shaper Features - Time aware traffic scheduler per port Switch Management Capabilities Comprehensive Configuration Registers Access - 10/100Mbps Ethernet switch basic functions: frame 2 - High-speed 4-wire SPI (up to 50MHz), I C interfaces buffer management, address look-up table, queue provide access to all internal registers management, MIB counters - MII Management (MIIM, MDC/MDIO 2-wire) Interface - Non-blocking store-and-forward switch fabric assures provides access to all PHY registers fast packet delivery by utilizing 4096 entry forwarding - In-band management via any of the data ports table with 256kByte frame buffer - I/O pin strapping facility to set certain register bits from - Jumbo packet support up to 9000 bytes I/O pins at reset time - Port mirroring/monitoring/sniffing: Power Management ingress and/or egress traffic to any port - IEEE 802.3az Energy Efficient Ethernet (EEE) - Rapid spanning tree protocol (RSTP) support for topol- - Energy detect power-down mode on cable disconnect ogy management and ring/linear recovery - Dynamic clock tree control - Multiple spanning tree protocol (MSTP) support - Unused ports can be individually powered down One External MAC Port with SGMII - Full-chip software power-down One External MAC Port with RGMII/MII/RMII - Wake-on-LAN (WoL) standby power mode with PME - RGMII v2.0, RMII v1.2 with 50MHz reference clock interrupt output for system wake upon triggered events input/output option, MII in PHY/MAC mode 2017 Microchip Technology Inc. DS00002391A-page 1KSZ8567S TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Documentation To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at: