Product Information

KSZ8895RQXCA

KSZ8895RQXCA electronic component of Microchip

Datasheet
Micrel Ethernet ICs 5-Port 10100 Ethernet Switch

Manufacturer: Microchip
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

5: USD 8.1375 ea
Line Total: USD 40.69

251 - Global Stock
Ships to you between
Tue. 21 May to Mon. 27 May
MOQ: 5  Multiples: 1
Pack Size: 1
Availability Price Quantity
251 - WHS 1


Ships to you between Tue. 21 May to Mon. 27 May

MOQ : 5
Multiples : 1

Stock Image

KSZ8895RQXCA
Microchip

5 : USD 8.1375
25 : USD 7.45
66 : USD 7.1375
132 : USD 7.0375
264 : USD 6.6875
528 : USD 6.5875
1056 : USD 6.4875
2508 : USD 6.3875

192 - WHS 2


Ships to you between Tue. 21 May to Mon. 27 May

MOQ : 1
Multiples : 1

Stock Image

KSZ8895RQXCA
Microchip

1 : USD 7.3357
25 : USD 7.3357

192 - WHS 3


Ships to you between Tue. 21 May to Mon. 27 May

MOQ : 2
Multiples : 1

Stock Image

KSZ8895RQXCA
Microchip

2 : USD 7.3357

768 - WHS 4


Ships to you between Tue. 21 May to Mon. 27 May

MOQ : 5
Multiples : 1

Stock Image

KSZ8895RQXCA
Microchip

5 : USD 8.1696

61 - WHS 5


Ships to you between Tue. 21 May to Mon. 27 May

MOQ : 63
Multiples : 63

Stock Image

KSZ8895RQXCA
Microchip

63 : USD 15.0455

247 - WHS 6


Ships to you between Tue. 21 May to Mon. 27 May

MOQ : 10
Multiples : 5

Stock Image

KSZ8895RQXCA
Microchip

10 : USD 8.9474
25 : USD 8.7683

     
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KSZ8895MQX/RQX/FQX/MLX Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface Programmable Weighted Fair Queuing for Ratio Features Control Advanced Switch Features Re-Mapping of 802.1p Priority Field Per Port IEEE 802.1q VLAN Support for up to 128 Active Basis VLAN Groups (Full-Range 4096 of VLAN IDs) Integrated 5-Port 10/100 Ethernet Switch Static MAC Table Supports up to 32 Entries New Generation Switch with Five MACs and Five VLAN ID Tag/Untagged Options, Per Port Basis PHYs that are Fully Compliant with the IEEE IEEE 802.1p/q Tag Insertion or Removal on a Per 802.3u Standard Port Basis Based on Ingress Port (Egress) PHYs Designed with Patented Enhanced Mixed- Programmable Rate Limiting at the Ingress and Signal Technology Egress on a Per Port Basis Non-Blocking Switch Fabric Ensures Fast Packet Jitter-Free Per Packet Based Rate Limiting Sup- Delivery by Utilizing a 1K MAC Address Lookup port Table and a Store-and-Forward Architecture Broadcast Storm Protection with Percentage Con- On-Chip 64Kbyte Memory for Frame Buffering trol (Global and Per Port Basis) (Not Shared with 1K Unicast Address Table) IEEE 802.1d Rapid Spanning Tree Protocol RSTP Full-Duplex IEEE 802.3x Flow Control (PAUSE) Support with Force Mode Option Tail Tag Mode (1 Byte Added Before FCS) Sup- Half-Duplex Back Pressure Flow Control port at Port 5 to Inform the Processor Which HP Auto MDI/MDI-X and IEEE Auto Crossover Ingress Port Receives the Packet Support 1.4 Gbps High-Performance Memory Bandwidth SW-MII Interface Supports Both MAC Mode and and Shared Memory Based Switch Fabric with PHY Mode Fully Non-Blocking Configuration 7-Wire Serial Network Interface (SNI) Support for Dual MII with MAC 5 and PHY 5 on Port 5, SW5- Legacy MAC MII/RMII for MAC 5 and P5-MII/RMII for PHY 5 Per Port LED Indicators for Link, Activity, and 10/ Enable/Disable Option for Huge Frame Size up to 100 Speed 2000 Bytes Per Frame Register Port Status Support for Link, Activity, IGMP v1/v2 Snooping (IPv4) Support for Multicast Full-/Half-Duplex and 10/100 Speed Packet Filtering LinkMD Cable Diagnostic Capabilities IPv4/IPv6 QoS Support On-Chip Terminations and Internal Biasing Tech- Support Unknown Unicast/Multicast Address and nology for Cost Down and Lowest Power Con- Unknown VID Packet Filtering sumption Self-Address Filtering Switch Monitoring Features Comprehensive Configuration Register Access Port Mirroring/Monitoring/Sniffing: Ingress and/or Serial Management Interface (MDC/MDIO) to All Egress Traffic to Any Port or MII PHYs Registers and SMI Interface (MDC/MDIO) MIB Counters for Fully Compliant Statistics Gath- to All Registers ering 34 MIB Counters Per Port 2 High-Speed SPI (up to 25 MHz) and I C Master Loopback Support for MAC, PHY, and Remote Interface to all Internal Registers Diagnostic of Failure I/O Pins Strapping and EEPROM to Program Interrupt for the Link Change on Any Ports Selective Registers in Unmanaged Switch Mode Low-Power Dissipation Control Registers Configurable on the Fly (Port- Priority, 802.1p/d/q, AN) Full-Chip Hardware Power-Down Full-Chip Software Power-Down and Per Port QoS/CoS Packet Prioritization Support Software Power-Down Per Port, 802.1p and DiffServ-Based Energy-Detect Mode Support <100 mW Full-Chip 1/2/4-Queue QoS Prioritization Selection Power Consumption When All Ports Have No 2016 Microchip Technology Inc. DS00002246A-page 1KSZ8895MQX/RQX/FQX/MLX Activity Very-Low Full-Chip Power Consumption (<0.5W) in Standalone 5-Port, without Extra Power Con- sumption on Transformers Dynamic Clock Tree Shutdown Feature Voltages: Single 3.3V Supply with 3.3V V and DDIO Internal 1.2V LDO Controller Enabled, or External 1.2V LDO Solution - Analog V 3.3V Only DDAT -V Support 3.3V, 2.5V, and 1.8V DDIO - Low 1.2V Core Power Commercial Temperature Range: 0C to +70C Industrial Temperature Range: 40C to +85C Available in 128-pin PQFP and 128-pin LQFP, Lead-Free Packages Target Applications Typical VoIP Phone Set-Top/Game Box Industrial Control IPTV POF SOHO Residential Gateway Broadband Gateway/Firewall/VPN Integrated DSL/Cable Modem Wireless LAN Access Point + Gateway Standalone 10/100 5-Port Switch DS00002246A-page 2 2016 Microchip Technology Inc.

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8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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