Product Information

LAN91C111I-NS

LAN91C111I-NS electronic component of Microchip

Datasheet
Ethernet ICs Ethernet IC PHY IND TEMP

Manufacturer: Microchip
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 39.5715 ea
Line Total: USD 39.57

343 - Global Stock
Ships to you between
Thu. 23 May to Mon. 27 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
247 - WHS 1


Ships to you between Fri. 17 May to Thu. 23 May

MOQ : 1
Multiples : 1

Stock Image

LAN91C111I-NS
Microchip

1 : USD 45.2375
5 : USD 41.45
10 : USD 40.825
25 : USD 39.2375
66 : USD 37.7375
132 : USD 37.1625
264 : USD 36.6125

343 - WHS 2


Ships to you between Thu. 23 May to Mon. 27 May

MOQ : 1
Multiples : 1

Stock Image

LAN91C111I-NS
Microchip

1 : USD 39.5715
25 : USD 36.041
100 : USD 34.822

106 - WHS 3


Ships to you between Fri. 17 May to Thu. 23 May

MOQ : 1
Multiples : 1

Stock Image

LAN91C111I-NS
Microchip

1 : USD 46.345
5 : USD 40.768

3841 - WHS 4


Ships to you between Fri. 17 May to Thu. 23 May

MOQ : 66
Multiples : 66

Stock Image

LAN91C111I-NS
Microchip

66 : USD 37.206
264 : USD 36.4619

     
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LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY Highlights Network Interface Single Chip Ethernet Controller Fully Integrated IEEE 802.3/802.3u-100Base-TX/ 10Base-T Physical Layer Dual Speed - 10/100 Mbps Auto-Negotiation: 10/100, Full / Half Duplex Fully Supports Full Duplex Switched Ethernet On Chip Wave Shaping - No External Filters Supports Burst Data Transfer Required 8 Kbytes Internal Memory for Receive and Trans- Adaptive Equalizer mit FIFO Buffers Baseline Wander Correction Enhanced Power Management Features LED Outputs (User selectable Up to 2 LED func- Optional Configuration via Serial EEPROM Inter- tions at one time) face -Link Supports 8, 16 and 32 Bit CPU Accesses - Activity Internal 32 Bit Wide Data Path (Into Packet Buffer Memory) - Full Duplex Built-in Transparent Arbitration for Slave Sequen- - 10/100 tial Access Architecture -Transmit Flat MMU Architecture with Symmetric Transmit - Receive and Receive Structures and Queues 3.3V Operation with 5V Tolerant IO Buffers (See Pin List Description for Additional Details) Single 25 MHz Reference Clock for Both PHY and MAC External 25Mhz-output pin for an external PHY supporting PHYs physical media. Low Power CMOS Design Supports Multiple Embedded Processor Host Interfaces -ARM -SH -Power PC - Coldfire - 680X0, 683XX - MIPS R3000 3.3V MII (Media Independent Interface) MAC- PHY Interface Running at Nibble Rate MII Management Serial Interface 128-Pin QFP RoHS compliant package 128-Pin TQFP 1.0 mm height RoHS compliant package Commercial Temperature Range from 0 C to 70C (LAN91C111) Industrial Temperature Range from -40 C to 85C (LAN91C111i) 2011-2016 Microchip Technology Inc. DS00002276A-page 1LAN91C111 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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