LAN9312 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface - Full duplex flow control Highlights - Backpressure (forced collision) half duplex High performance and full featured 2 port switch flow control with VLAN, QoS packet prioritization, Rate Limit- - Automatic flow control based on programma- ing, IGMP monitoring and management functions ble levels Easily interfaces to most 32-bit embedded CPUs - Automatic 32-bit CRC generation and check- Unique Virtual PHY feature simplifies software ing development by mimicking the multiple switch - Automatic payload padding ports as a single port MAC/PHY - 2K Jumbo packet support Integrated IEEE 1588 Hardware Time Stamp Unit - Programmable interframe gap, flow control pause value Target Applications - Full transmit/receive statistics Cable, satellite, and IP set-top boxes - Auto-negotiation Digital televisions - Automatic MDI/MDI-X Digital video recorders - Loop-back mode VoIP/Video phone systems High-performance host bus interface Home gateways - Provides in-band network communication Test/Measurement equipment path Industrial automation systems - Access to management registers Key Benefits - Simple, SRAM-like interface - 32-bit data bus Ethernet Switch Fabric - Big, little, and mixed endian support - 32K buffer RAM - Large TX and RX FIFOs for high latency - 1K entry forwarding table applications - Port based IEEE 802.1Q VLAN support (16 - Programmable water marks and threshold groups) levels - Programmable IEEE 802.1Q tag insertion/removal - Host interrupt support - IEEE 802.1d spanning tree protocol support IEEE 1588 Hardware Time Stamp Unit - QoS/CoS Packet prioritization - 4 dynamic QoS queues per port - Global 64-bit tunable clock - Input priority determined by VLAN tag, DA lookup, - Master or slave mode per port TOS, DIFFSERV or port default value - Time stamp on TX or RX of Sync and - Programmable class of service map based on input Delay req packets per port, Timestamp on priority GPIO - Remapping of 802.1Q priority field on per port basis - 64-bit timer comparator event generation - Programmable rate limiting at the ingress/egress (GPIO or IRQ) ports with random early discard, per port / priority Comprehensive Power Management Features - IGMP v1/v2/v3 monitoring for Multicast - Wake on LAN packet filtering - Wake on link status change (energy detect) - Programmable filter by MAC address - Magic packet wakeup Switch Management - Wakeup indicator event signal - Port mirroring/monitoring/sniffing: ingress Other Features and/or egress traffic on any ports or port pairs - General Purpose Timer - Fully compliant statistics (MIB) gathering 2 - Serial EEPROM interface (I C master or counters Microwire master) for non-managed config- - Control registers configurable on-the-fly uration Ports - Programmable GPIOs/LEDs - 2 internal 10/100 PHYs with HP Auto-MDIX Single 3.3V power supply support Available in Commercial Temp. Range - Fully compliant with IEEE 802.3 standards - 10BASE-T and 100BASE-TX support - Full and half duplex support 2008-2016 Microchip Technology Inc. DS00002287A-page 1LAN9312 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: