LAN9355 3-Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII Ports Highlights - Port 0: MII MAC, MII PHY, RMII PHY, RMII MAC modes High performance 3-port switch with VLAN, QoS - Port 1: Internal PHY, MII MAC, MII PHY, RMII MAC, packet prioritization, rate limiting, IGMP monitoring RMII PHY modes and management functions - Port 2: Internal PHY - 2 internal 10/100 PHYs with HP Auto-MDIX Interfaces at up to 200Mbps via Turbo MII support Integrated Ethernet PHYs with HP Auto-MDIX - 200Mbps Turbo MII (PHY or MAC mode) Compliant with Energy Efficient Ethernet 802.3az - Fully compliant with IEEE 802.3 standards Wake on LAN (WoL) support - 10BASE-T and 100BASE-TX support Integrated IEEE 1588v2 hardware time stamp unit - 100BASE-FX support via external fiber transceiver Cable diagnostic support - Full and half duplex support, full duplex flow control 1.8V to 3.3V variable voltage I/O - Backpressure (forced collision) half duplex flow control Integrated 1.2V regulator for single 3.3V operation - Automatic flow control based on programmable levels - Automatic 32-bit CRC generation and checking - Programmable interframe gap, flow control pause value Target Applications - Auto-negotiation, polarity correction & MDI/MDI-X Cable, satellite, and IP set-top boxes IEEE 1588v2 hardware time stamp unit Digital televisions & video recorders - Global 64-bit tunable clock VoIP/Video phone systems, home gateways - Boundary clock: master / slave, one-step / two-step, end-to-end / peer-to-peer delay Test/Measurement equipment, industrial automation - Transparent Clock with Ordinary Clock: master / slave, one-step / two-step, end-to-end / peer- Key Benefits to-peer delay - Fully programmable timestamp on TX or RX, Ethernet Switch Fabric timestamp on GPIO - 32K buffer RAM, 512 entry forwarding table - 64-bit timer comparator event generation (GPIO or IRQ) - Port based IEEE 802.1Q VLAN support (16 groups) Comprehensive power management features - Programmable IEEE 802.1Q tag insertion/removal - IEEE 802.1D spanning tree protocol support - 3 power-down levels - 4 separate transmit queues available per port - Wake on link status change (energy detect) - Fixed or weighted egress priority servicing - Magic packet wakeup, Wake on LAN (WoL), wake on - QoS/CoS Packet prioritization broadcast, wake on perfect DA - Input priority determined by VLAN tag, DA lookup, TOS, - Wakeup indicator event signal DIFFSERV or port default value Power and I/O - Programmable Traffic Class map based on input priority - Integrated power-on reset circuit on per port basis - Remapping of 802.1Q priority field on per port basis - Latch-up performance exceeds 150mA - Programmable rate limiting at the ingress with coloring per EIA/JESD78, Class II and random early discard, per port / priority - JEDEC Class 3A ESD performance - Programmable rate limiting at the egress with leaky - Single 3.3V power supply bucket algorithm, per port / priority (integrated 1.2V regulator) - IGMP v1/v2/v3 monitoring for Multicast packet filtering - Programmable broadcast storm protection with global % Additional Features control and enable per port - Multifunction GPIOs - Programmable buffer usage limits - Ability to use low cost 25MHz crystal for reduced BOM - Dynamic queues on internal memory Packaging - Programmable filter by MAC address - Pb-free RoHS compliant 88-pin QFN or 80-pin TQFP- Switch Management EP - Port mirroring/monitoring/sniffing: ingress and/or egress Available in commercial and industrial temp. ranges traffic on any port or port pair - Fully compliant statistics (MIB) gathering counters 2015 Microchip Technology Inc. DS00001927A-page 1LAN9355 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Documentation To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at: