MCP3910 3V Two-Channel Analog Front End Features: Description: The MCP3910 is a 3V two-channel Analog Front End Two Synchronous Sampling 24-Bit Resolution (AFE), containing two synchronous sampling Delta-Sigma A/D Converters Delta-Sigma, Analog-to-Digital Converters (ADC), two 93.5 dB SINAD, -107 dBc Total Harmonic Programmable Gain Amplifiers (PGA), phase delay th Distortion (THD) (up to 35 harmonic), 112 dB compensation block, low-drift internal voltage Spurious-Free Dynamic Range (SFDR) for Each reference, Digital Offset and Gain Errors Calibration Channel registers and high-speed 20MHz SPI-compatible Flexible Serial Interface that Includes Both SPI serial interface. and a Simple Two-Wire Interface Ideal for The MCP3910 ADCs are fully configurable with Polyphase Shunt Energy Meters features such as: 16-/24-bit resolution, Oversampling Enables 0.1% Typical Active Power Measurement Ratio (OSR) from 32 to 4096, gain from 1x to 32x, Error Over a 10,000:1 Dynamic Range independent shutdown and Reset, dithering and Advanced Security Features: auto-zeroing. Communication is largely simplified with - 16-Bit Cyclic Redundancy Check (CRC) 8-bit commands, including various continuous Read/ Checksum on All Communications for Secure Write modes and 16-/24-/32-bit data formats that can Data Transfers be accessed by the Direct Memory Access (DMA) of an 8, 16 or 32-bit MCU. It also includes a separate Data - 16-Bit Cyclic Redundancy Check (CRC) Ready pin that can directly be connected to an Interrupt Checksum and Interrupt Alert for Register Request (IRQ) input of an MCU. Map Configuration The MCP3910 includes advanced security features to - Register Map Lock with 8-Bit Secure Key secure the communications and the configuration set- 2.7V-3.6V AV , DV DD DD tings, such as a CRC-16 checksum on both serial data Programmable Data Rate, Up to 125 ksps: outputs and on the static register map configuration. It - 4 MHz Maximum Sampling Frequency also includes a register map lock through an 8-bit - 16 MHz Maximum Master Clock password to stop unwanted WRITE commands from processing. Oversampling Ratio, Up to 4096 For polyphase shunt-based energy meters, the Ultra Low-Power Shutdown Mode with < 10 A MCP3910 two-wire serial interface greatly reduces -122 dB Crosstalk between Channels system cost, requiring only a single bidirectional Low-Drift 1.2V Internal Voltage Reference: isolator per phase. 9 ppm/C The MCP3910 is capable of interfacing a variety of volt- Differential Voltage Reference Input Pins age and current sensors, including shunts, current High-Gain Programmable Gain Amplifier (PGA) transformers, Rogowski coils and Hall effect sensors. on Each Channel (up to 32 V/V) Phase Delay Compensation with 1 s Time Applications: Resolution Single-Phase and Polyphase Energy Meters Separate Data Ready Pin for Easy Synchronization Energy Metering and Power Measurement Individual 24-Bit Digital Offset and Gain Error Automotive Correction for Each Channel Portable Instrumentation High-Speed 20 MHz SPI Interface with Mode 0,0 Medical and Power Monitoring and 1,1 Compatibility Audio/Voice Recognition Continuous Read/Write Modes for Minimum Isolated Sensor Applications Communication with Dedicated 16-/32-Bit Modes Available in 20-Lead QFN and SSOP Packages Extended Temperature Range: -40C to +125C (All Specifications are Valid Down to -45C Operation) 2012-2020 Microchip Technology Inc. DS20005116D-page 1MCP3910 Package Type MCP3910 MCP3910 SSOP 4x4QFN* RESET/OSR0 1 20 SDI/OSR1 DV 2 19 SDO DD AV 3 18 SCK/MCLK DD CH0+ 4 17 CS/BOOST CH0- 5 16 OSC2/MODE 20 19 18 17 16 CH1- 15 6 OSC1/CLKI/GAIN0 CH0+ 1 15 SCK/MCLK CH1+ 7 14 DR/GAIN1 14 CS/BOOST CH0- 2 A 8 13 MDAT0 EP GND 13 3 OSC2/MODE CH1- 21 12 MDAT1 REFIN+/OUT 9 12 D OSC1/CLKI/GAIN0 REFIN- 11 CH1+ 4 10 GND 11 DR/GAIN1 A 5 GND 67 8 9 10 * Includes Exposed Thermal Pad (EP) see Table 3-1. Functional Block Diagram AV DV DD DD REFIN+/OUT Voltage VREFEXT AMCLK Xtal Oscillator Reference OSC1/CLKI/GAIN0 MCLK Clock + V Generation REF OSC2/MODE DMCLK/DRCLK REFIN- V - V + ANALOG DIGITAL REF REF OSR 2:0 DMCLK PRE 1:0 3 SINC + OFFCAL CH0 GAINCAL CH0 1 SINC 23:0 23:0 CH0+ + MOD<3:0> DATA CH0 + X 23:0 CH0- DR/GAIN1 PGA SDO Modulator Phase PHASE 11:0 Digital Shifter Interfaces RESET/OSR0 OFFCAL CH1 GAINCAL CH1 (SPI & Two-Wire) SDI/OSR1 23:0 23:0 CH1+ SCK + MOD<7:4> DATA CH1 + X CS/BOOST 23:0 CH1- 3 PGA SINC + 1 Modulator SINC EN MDAT DUAL ADC MDAT0 Modulator MOD 7:0 Output Block MDAT1 POR POR AV DV DD DD Monitoring Monitoring A D GND GND DS20005116D-page 2 2012-2020 Microchip Technology Inc. AV REFIN+/OUT DD DV REFIN- DD D RESET/OSR0 GND SDI/OSR1 MDAT1 SDO MDAT0