MEC1725N-B0-I/LJ Microchip

MEC1725 Keyboard and Embedded Controller for Notebook PC - External single-ended 32 kHz clock Operating Conditions source Operating Voltages: 3.3 V and 1.8 V o o Package Options C to 85 C Operating Temperature Range: -40 - 176 pin WFBGA Low Power Modes Security Features Chip is designed to always operate in Lowest Power state during Normal Operation Boot ROM Secure Boot Loader Supports all 5 ACPI Power States for PC plat- - Hardware Root of Trust (RoT) using Secure forms Boot and Immutable code Supports 2 Chip-level Sleep Modes: Light Sleep - Supports 2 Code Images in external SPI and Heavy Sleep Flash (Primary and Fall back image) - Low Standby Current in Sleep Modes - Authenticates SPI Flash image before load- ing ARM Cortex-M4F Embedded Processor - Support AES-256 Encrypted SPI Flash Programmable clock frequency up to 48 MHz images Fixed point processor Hardware Accelerators: Single 4GByte Addressing Space - Multi purpose AES Crypto Engine: Nested Vectored Interrupt Controller (NVIC) - Support for 128-bit - 256-bit key length - Maskable Interrupt Controller - Supports Battery Authentication applica- - Maskable hardware wake up events tions - 8 Levels of priority, individually assignable by - Digital Signature Algorithm Support vector - Support for ECDSA and EC KCDSA EC Interrupt Aggregator expands number of Inter- - Cryptographic Hash Engine rupt sources supported or reduces number of vec- - Support for SHA-1, SHA-256 to SHA-512 tors needed - Public Key Crypto Engine Standard debug support Complete ARM - Hardware support for RSA and Elliptic - JTAG-Based DAP port, comprised of SWJ- Curve asymmetric public key algorithms DP and AHB-AP debugger access functions - RSA keys length of 1024 to 4096 bits Memory Components - ECC Prime Field keys up to 571 bits - 416KB Code/Data SRAM - ECC Binary Field keys up to 571 bits - 352KB optimized for code performance - Microcoded support for standard public - 64KB optimized for data performance key algorithms - 128 Bytes Battery Powered Storage SRAM - OTP for storing Keys and IDs -4K bits OTP - Lockable on 32 B boundaries to prevent read access or write access - In circuit programmable -ROM - True Random Number Generator - 1 Kbit FIFO - Contains Boot ROM - JTAG Disabled by default - Contains Runtime APIs for built-in func- tions System Host interface - 128KB of ROM space Enhanced Serial Peripheral Interface (eSPI) Clocks - Intel eSPI Specification compliant 96 MHz Internal PLL - eSPI Interface Base Spec, Intel Doc. 327432-004, Rev. 1.0. 32 kHz Clock Sources - eSPI Compatibility Spec, Intel Doc. - Internal 32 kHz silicon oscillator 562633, Rev. 0.6 2020-2021 Microchip Technology Inc. DS00003584E-page 1MEC1725 - Support for Master Attached Flash Sharing - Two Ports, Assignable to Any eSPI IO (MAFS) Address - Support for Slave Attached Flash Sharing - 24-bit Timestamp with Adjustable Timebase (SAFS) - 16-Entry FIFO - Supports all four channels: Peripheral Features - Peripheral Channel Internal DMA Controller - Virtual Wires Channel - Hardware or Firmware Flow Control - Out-of-Band (OOB) Tunneled Message - Firmware Initiated Memory-to-Memory trans- Channel fers - Run-time Flash Access Channel - Hardware CRC-32 Generator on Channel 0 - Supports EC Bus Master to Host Memory I2C/SMBus Controllers - Supports up to 66 MHz maximum operating - 5 I2C/SMBus controllers frequency - 15 Configurable I2C ports One Serial Peripheral Interface (SPI) Slave - Full Crossbar switch allows any port to be - Quad SPI (half-duplex) or Single wire (full connected to any controller duplex) support - Supports Promiscuous mode of operation - Mode 0 and Mode3 operation - Fully Operational on Standby Power - Programmable wait time for response delay - Multi-Master Capable System to EC Message Interface - Supports Clock Stretching - Three Embedded Memory Interfaces - Programmable Bus Speeds - Provides Two Windows to On-Chip SRAM - 1 MHz Capable for Host Access - Supports DMA Network Layer - Two Register Mailbox Command Interface - Mailbox Registers Interface General Purpose I/O Pins - Inputs - Thirty-two 8-bit registers - Asynchronous rising and falling edge - Two Register Mailbox Command Inter- wakeup detection Interrupt High or Low faces Level - Two Register SMI Source Interfaces -Outputs: - Six ACPI Embedded Controller Interfaces - Push Pull or Open Drain output - Five EC Interfaces - Programmable power well emulation - One Power Management Interface - Pull up or pull down resistor control One Serial Peripheral Interface (SPI) Master Con- - Automatically disabling pull-up resistors troller when output driven low - Dual and Quad I/O Support - Automatically disabling pull-down resis- - Flexible Clock Rates tors when output driven high - Support for 1.8V and 3.3V slave devices - Programmable drive strength - SPI Burst Capable - Two separate1.8V/3.3V configurable IO - SPI Controller Operates with Internal DMA regions Controller with CRC Generation - Group or individual control of GPIO data - Mappable to the following ports (only 1 port - 13- Over voltage tolerant GPIO pins active at a time) - Glitch protection and Under-Voltage Protec- - 1 shared SPI Interface tion on all GPIO pins - 1 Private SPI Interface - 8 GPIO Pass through ports Two General purpose Serial Peripheral Interface Input Capture and Compare timer (SPI) Controllers - Six 32-bit Capture Registers - One EC driven Full Duplex Serial Communi- - 16 Input Pins (ICTx) cation Interface - Full Crossbar switch allows any port to be - Flexible Clock Rates connected to any controller - SPI burst capable - 32-bit Free-running timer PECI Interface 3.1 - Two 32-bit Compare Registers - Support Intels low voltage PECI - Capture, Compare and Overflow Interrupts Port 80 BIOS Debug Port DS00003584E-page 2 2020-2021 Microchip Technology Inc.