Product Information

P1AFS1500-2FGG484

P1AFS1500-2FGG484 electronic component of Microchip

Datasheet
FPGA - Field Programmable Gate Array Fusion

Manufacturer: Microchip
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

60: USD 418.5018 ea
Line Total: USD 25110.11

0 - Global Stock
MOQ: 60  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - WHS 1


Ships to you between Wed. 08 May to Tue. 14 May

MOQ : 60
Multiples : 1
60 : USD 418.5018

     
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Revision 6 Fusion Family of Mixed Signal FPGAs In-System Programming (ISP) and Security Features and Benefits ISP with 128-Bit AES via JTAG High-Performance Reprogrammable Flash FlashLock Designed to Protect FPGA Contents Technology Advanced Digital I/O Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Process Bank-Selectable I/O Voltages Up to 5 Banks per Chip Nonvolatile, Retains Program when Powered Off Single-Ended I/O Standards: LVTTL, LVCMOS Instant On Single-Chip Solution 3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and 350 MHz System Performance LVCMOS 2.5 V / 5.0 V Input Embedded Flash Memory Differential I/O Standards: LVPECL, LVDS, B-LVDS, M-LVDS User Flash Memory 2 Mbits to 8 Mbits Built-In I/O Registers Configurable 8-, 16-, or 32-Bit Datapath 700 Mbps DDR Operation 10 ns Access in Read-Ahead Mode Hot-Swappable I/Os 1 Kbit of Additional FlashROM Programmable Output Slew Rate, Drive Strength, and Integrated A/D Converter (ADC) and Analog I/O Weak Pull-Up/Down Resistor Up to 12-Bit Resolution and up to 600 Ksps Pin-Compatible Packages across the Fusion Family Internal 2.56 V or External Reference Voltage SRAMs and FIFOs ADC: Up to 30 Scalable Analog Input Channels Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (1, 2, High-Voltage Input Tolerance: 10.5 V to +12 V 4, 9, and 18 organizations available) Current Monitor and Temperature Monitor Blocks True Dual-Port SRAM (except 18) Up to 10 MOSFET Gate Driver Outputs Programmable Embedded FIFO Control Logic P- and N-Channel Power MOSFET Support Programmable 1, 3, 10, 30 A, and 20 mA Drive Soft ARM Cortex-M1 Fusion Devices (M1) Strengths ARM Cortex-M1Enabled ADC Accuracy is Better than 1% Pigeon Point ATCA IP Support (P1) On-Chip Clocking Support Targeted to Pigeon Point Board Management Internal 100 MHz RC Oscillator (accurate to 1%) Reference (BMR) Starter Kits Crystal Oscillator Support (32 KHz to 20 MHz) Designed in Partnership with Pigeon Point Systems Programmable Real-Time Counter (RTC) ARM Cortex-M1 Enabled 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated MicroBlade Advanced Mezzanine Card Support (U1) PLLs Targeted to Advanced Mezzanine Card (AdvancedMC Phase Shift, Multiply/Divide, and Delay Capabilities Designs) Frequency: Input 1.5350 MHz, Output 0.75350 Designed in Partnership with MicroBlade MHz 8051-Based Module Management Controller (MMC) Low Power Consumption Single 3.3 V Power Supply with On-Chip 1.5 V Regulator Sleep and Standby Low-Power Modes Table 1 Fusion Family Fusion Devices AFS090 AFS250 AFS600 AFS1500 * ARM Cortex-M1 Devices M1AFS250 M1AFS600 M1AFS1500 Pigeon Point Devices P1AFS600 P1AFS1500 MicroBlade Devices U1AFS250 U1AFS600 U1AFS1500 System Gates 90,000 250,000 600,000 1,500,000 Tiles (D-flip-flops) 2,304 6,144 13,824 38,400 General Secure (AES) ISP Yes Yes Yes Yes Information PLLs 11 22 Globals 18 18 18 18 Flash Memory Blocks (2 Mbits) 1 1 2 4 Total Flash Memory Bits 2M 2M 4M 8M Memory FlashROM Bits 1,024 1,024 1,024 1,024 RAM Blocks (4,608 bits) 6 8 24 60 RAM kbits 27 36 108 270 Analog Quads 5 6 10 10 Analog Input Channels 15 18 30 30 Gate Driver Outputs 5 6 10 10 Analog and I/Os I/O Banks (+ JTAG) 4 4 5 5 Maximum Digital I/Os 75 114 172 252 Analog I/Os 20 24 40 40 Note: *Refer to the Cortex-M1 product brief for more information. March 2014 I 2014 Microsemi CorporationBank 2 Fusion Family of Mixed Signal FPGAs Fusion Device Architecture Overview Bank 0 Bank 1 CCC SRAM Block 4,608-Bit Dual-Port SRAM or FIFO Block OSC I/Os CCC/PLL VersaTile SRAM Block 4,608-Bit Dual-Port SRAM ISP AES User Nonvolatile Charge Pumps or FIFO Block Decryption FlashROM Flash Memory Blocks ADC Flash Memory Blocks Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Quad Quad Quad Quad Quad Quad Quad Quad Quad Quad CCC Bank 3 Figure 1 Fusion Device Architecture Overview (AFS600) Package I/Os: Single-/Double-Ended (Analog) Fusion Devices AFS090 AFS250 AFS600 AFS1500 ARM Cortex-M1 Devices M1AFS250 M1AFS600 M1AFS1500 1 1 Pigeon Point Devices P1AFS600 P1AFS1500 2 2 2 MicroBlade Devices U1AFS250 U1AFS600 U1AFS1500 3 QN108 37/9 (16) 3 QN180 60/16 (20) 65/15 (24) 4 PQ208 93/26 (24) 95/46 (40) FG256 75/22 (20) 114/37 (24) 119/58 (40) 119/58 (40) FG484 172/86 (40) 223/109 (40) FG676 252/126 (40) Notes: 1. Pigeon Point devices are only offered in FG484 and FG256. 2. MicroBlade devices are only offered in FG256. 3. Package not available. 4. Fusion devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600). II Revision 6 Bank 4

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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