PIC24F16KL402-IMQ

PIC24F16KL402 FAMILY Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with XLP Technology Power Management Modes: Peripheral Features: High-Current Sink/Source (18 mA/18 mA) on All Run CPU, Flash, SRAM and Peripherals On I/O Pins Doze CPU Clock Runs Slower than Peripherals Configurable Open-Drain Outputs on Digital I/O Pins Idle CPU Off, SRAM and Peripherals On Up to Three External Interrupt Sources Sleep CPU, Flash and Peripherals Off and SRAM On Two 16-Bit Timer/Counters with Selectable Clock Low-Power Consumption: Sources - Run mode currents of 150 A/MHz typical at 1.8V Up to Two 8-Bit Timers/Counters with Programmable - Idle mode currents under 80 A/MHz at 1.8V Prescalers - Sleep mode currents as low as 30 nA at +25C Two Capture/Compare/PWM (CCP) modules: - Watchdog Timer as low as 210 nA at +25C - Modules automatically configure and drive I/O - 16-bit Capture with max. resolution 40 ns High-Performance CPU: - 16-bit Compare with max. resolution 83.3 ns Modified Harvard Architecture - 1-bit to 10-bit PWM resolution Up to 16 MIPS Operation 32 MHz Up to One Enhanced CCP module: 8 MHz Internal Oscillator: - Backward compatible with CCP - 4x PLL option - 1, 2 or 4 PWM outputs - Multiple divide options - Programmable dead time 17-Bit x 17-Bit Single-Cycle Hardware - Auto-shutdown on external event Fractional/integer Multiplier Up to Two Master Synchronous Serial Port modules 32-Bit by 16-Bit Hardware Divider (MSSPs) with Two Modes of Operation: 16 x 16-Bit Working Register Array - 3-wire SPI (all four modes) C Compiler Optimized Instruction Set 2 -I C Master, Multi-Master and Slave modes and Architecture (ISA): 7-Bit/10-Bit Addressing - 76 base instructions Up to Two UART modules: - Flexible addressing modes - Supports RS-485, RS-232 and LIN/J2602 Linear Program Memory Addressing - On-chip hardware encoder/decoder for IrDA Linear Data Memory Addressing - Auto-wake-up on Start bit Two Address Generation Units (AGU) for Separate - Auto-Baud Detect (ABD) Read and Write Addressing of Data Memory - Two-byte transmit and receive FIFO buffers Memory Peripherals Flash Data Device Pins Data Program EEPROM (bytes) (bytes) (bytes) PIC24F16KL402 28 16K 1024 512 12 2 2/2 2/1 2 2 Y PIC24F08KL402 28 8K 1024 512 12 2 2/2 2/1 2 2 Y PIC24F16KL401 20 16K 1024 512 12 2 2/2 2/1 2 2 Y PIC24F08KL401 20 8K 1024 512 12 2 2/2 2/1 2 2 Y PIC24F08KL302 28 8K 1024 256 2 2/2 2/1 2 2 Y PIC24F08KL301 20 8K 1024 256 2 2/2 2/1 2 2 Y PIC24F08KL201 20 8K 512 12 1 1/2 2/0 1 1 Y PIC24F08KL200 14 8K 512 7 1 1/2 2/0 1 1 Y PIC24F04KL101 20 4K 512 1 1/2 2/0 1 1 Y PIC24F04KL100 14 4K 512 1 1/2 2/0 1 1 Y 2011-2013 Microchip Technology Inc. DS30001037C-page 1 10-Bit A/D (ch) Comparators 8/16-Bit Timers CCP/ECCP MSSP UART w/IrDA Ultra Low-Power Wake-upPIC24F16KL402 FAMILY Fail-Safe Clock Monitor (FSCM) Operation: Analog Features: - Detects clock failure and switches to on-chip, 10-Bit, up to 12-Channel Analog-to-Digital (A/D) Low-Power RC (LPRC) oscillator Converter: Power-on Reset (POR), Power-up Timer (PWRT) - 500 ksps conversion rate and Oscillator Start-up Timer (OST) - Conversion available during Sleep and Idle Flexible Watchdog Timer (WDT): Dual Rail-to-Rail Analog Comparators with - Uses its own Low-Power RC oscillator Programmable Input/Output Configuration - Windowed operating modes On-Chip Voltage Reference - Programmable period of 2 ms to 131s In-Circuit Serial Programming (ICSP) and Special Microcontroller Features: In-Circuit Emulation (ICE) via 2 Pins Operating Voltage Range of 1.8V to 3.6V Programmable High/Low-Voltage Detect (HLVD) 10,000 Erase/Write Cycle Endurance Flash Program Programmable Brown-out Reset (BOR): Memory, Typical - Configurable for software controlled operation and 100,000 Erase/Write Cycle Endurance Data shutdown in Sleep mode EEPROM, Typical - Selectable trip points (1.8V, 2.7V and 3.0V) Flash and Data EEPROM Data Retention: - Low-power 2.0V POR re-arm 40 Years Minimum Self-Programmable under Software Control Programmable Reference Clock Output DS30001037C-page 2 2011-2013 Microchip Technology Inc.