PL133-67 Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC FEATURES DESCRIPTION The PL133-67 is an advanced fanout buffer design for 1:6 LVCMOS output fanout buffer for DC to 150MHz high performance, low-power, small form factor applica- 8mA Output Drive Strength tions. The PL133-67 accepts a reference clock input from Low power consumption for portable applications DC to 150MHz and provides 6 outputs of the same fre- Low input-output delay quency. Output-Output skew less than 250ps The PL133-67 is offered in a TSSOP-16L package and it Low Additive Phase Jitter of 60fs RMS offers the best phase noise, additive jitter performance, 2.5V to 3.3V, 10% operation and lowest power consumption of any comparable IC. Operating temperature range from -40C to 85C Available in 16-Pin SOP GREEN/RoHS package The PL133-67 outputs can be disabled to a high imped- ance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled. BLOCK DIAGRAM AND PACKAGE PINOUT REF 1 16 DNC CLK1 DNC 2 15 DNC CLK0 3 14 CLK5 CLK2 VDD 4 13 VDD CLK3 REF GND 5 12 GND CLK4 CLK1 6 11 CLK4 CLK5 CLK2 7 10 CLK3 OE 8 9 GND CLK6 OE TSSOP-16L Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1(408) 944 -0800 fax +1(408) 474-1000 www.micrel.com Rev 03/18/11 Page 1 PL133-67 Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC PIN DESCRIPTIONS Name TSSOP-16L Type Description REF 1 I Input reference frequency. CLK0 3 O Buffered clock output CLK1 6 O Buffered clock output CLK2 7 O Buffered clock output CLK3 10 O Buffered clock output CLK4 11 O Buffered clock output CLK5 14 O Buffered clock output VDD 4, 13 P VDD connection GND 5, 9, 12 P GND connection OE 8 I Output Enable Control Input with 130K Pull-Up DNC 2, 8, 15, 16 - Do Not Connect LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB d esign: Signal Integrity and Termination Decoupling and Power Supply Considerations Considerations - Keep traces short - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power - Trace = Inductor. With a capacitive load this equals supply ringing - Addition of a ferrite bead in series with VDD can - Long trace = Transmission Line. Without proper termi- help prevent noise from other board sources nation this will cause reflections ( looks like ringing ). - Value of decoupling capacitor is frequency de- - Design long traces (> 1 inch) as striplines or pendant. Typical values to use are 0.1 F for de- microstrips with defined impedance. signs using frequencies < 50MHz and 0.01 F for - Match trace at one side to avoid reflections bouncing designs using frequencies > 50MHz. back and forth. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer To CMOS Input ( Typical buffer impedance 20 ohm) 50 ohm line Connect a 33 ohm series resistor at each of the output clocks to enhance the stability of the output signal Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax +1(408) 474-1000 www.micrel.com Rev 03/18/11 Page 2