PL620-8x PL620-88/-89 Low Phase Noise XO (9.5-65MHz Output) FEATURES PIN CONFIGURATION Crystal input range: 19MHz to 65MHz VDD 1 16 DNC Output range: 9.5MHz 65MHz Very low phase noise and jitter XIN 2 15 DNC Complementary outputs: XOUT 3 14 GNDBUF o LVPECL (PL620-88) DNC 4 13 QBAR o LVDS (PL620-89) Supports 2.5V or 3.3V Power Supply. S2 5 12 VDDBUF Available in 16 pin TSSOP GREEN/RoHS OE 6 11 Q compliant package. DNC 7 10 GNDBUF GND 8 9 GND TSSOP-16L Note: denotes internal pull up OUTPUT ENABLE LOGIC TABLE DESCRIPTION The PL620-88 (LVPECL) and PL620-89 (LVDS) are Part Number OE State XO ICs specifically designed to work with rd 0 (Default) Output enabled fundamental or 3 OT crystals between 19MHz and PL620-88 65MHz. The selectable divide by two feature extends 1 Tri-state the output range from 9.5MHz to 65MHz. They 0 Tri-state require very low current into the crystal resulting in PL620-89 better overall stability. 1 (Default) Output enabled OUTPUT FREQUENCY DIVIDE BY BLOCK DIAGRAM TWO SELECTOR (S2) S2 Output O 0 Intput/2 E Q 1(Default) Input Q Oscillator Amplifier X+ S2 X- Micrel Inc. 2180 Fortune Drive S an Jose, CA 95131 USA tel +1(408) 944-0800 fax +1(408) 474-1000 www.micrel.com Rev 4/28/09 Page 1 PL620-88/-89 Low Phase Noise XO (9.5-65MHz Output) PACKAGE PIN ASSIGNMENT Name Pin Description VDD 1 Power Supply. XIN 2 Crystal input. See Crystal Specification on page 3. XOUT 3 Crystal output. See Crystal Specification on page 3. DNC 4, 7, 15, 16 Do Not Connect. Output Divide by Two selector pin. See the OUTPUT DIVIDE BY TWO S2 5 SELECTOR table on page 1. OE 6 Output Enable input. See OUTPUT ENABLE LOGIC table on page 1. GND 8, 9 Ground. GNDBUF 10 Ground for output buffer circuitry. Q 11 LVPECL or LVDS output. VDDBUF 12 Power supply for output buffer circuitry. QBAR 13 Complementary LVPECL or LVDS output. GNDBUF 14 Ground for output buffer circuitry. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN MAX UNITS Supply Voltage V 4.6 V DD Input Voltage, dc V -0.5 V +0.5 V I DD Output Voltage, dc V -0.5 V +0.5 V O DD Storage Temperature T -65 150 C S Ambient Operating Temperature T -40 85 A C Junction Temperature T 125 C J Lead Temperature (soldering, 10s) 260 C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for exten ded periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other conditions above the operational limits noted in this speci fication is not implied. Micrel Inc. 2180 Fortune Drive S an Jose, CA 95131 USA tel +1(408) 944-0800 fax +1(408) 474-1000 www.micrel.com Rev 4/28/09 Page 2