8 Mbit (x16) Multi-Purpose Flash SST39WF800B Data Sheet FEATURES: Organized as 512K x16 Fast Erase and Word-Program Single Voltage Read and Write Operations Sector-Erase Time: 36 ms (typical) Block-Erase Time: 36 ms (typical) 1.65-1.95V Chip-Erase Time: 140 ms (typical) Superior Reliability Word-Program Time: 28 s (typical) Endurance: 100,000 Cycles (typical) Automatic Write Timing Greater than 100 years Data Retention Internal V Generation PP Low Power Consumption (typical values at 5 MHz) End-of-Write Detection Active Current: 5 mA (typical) Toggle Bit Standby Current: 5 A (typical) Data Polling Sector-Erase Capability CMOS I/O Compatibility Uniform 2 KWord sectors JEDEC Standard Block-Erase Capability Flash EEPROM Pinouts and command sets Uniform 32 KWord blocks Packages Available Fast Read Access Time 48-ball TFBGA (6mm x 8mm) 70 ns 48-ball WFBGA (4mm x 6mm) Micro-Package Latched Address and Data 48-ball XFLGA (5mm x 6mm) Micro-Package 48-ball XFLGA (4mm x 6mm) Micro-Package All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST39WF800B is a 512K x16 CMOS Multi-Purpose during Erase and Program than alternative flash technolo- Flash (MPF) manufactured with SST proprietary, high-per- gies. When programming a flash device, the total energy formance CMOS SuperFlash technology. The split-gate consumed is a function of the applied voltage, current, and cell design and thick-oxide tunneling injector attain better time of application. For any given voltage range, Super- reliability and manufacturability compared to alternate Flash technology uses less current to program and has a approaches. The SST39WF800B writes (Program or shorter erase time therefore, the total energy consumed Erase) with a 1.65-1.95V power supply. This device con- during any Erase or Program operation is less than alterna- forms to JEDEC standard pin assignments for x16 memo- tive flash technologies. These devices also improve flexibil- ries. ity while lowering the cost for program, data, and configuration storage applications. The SST39WF800B features high-performance Word-Pro- gramming which provides a typical Word-Program time of SuperFlash technology provides fixed Erase and Program 28 sec. It uses Toggle Bit or Data Polling to detect the times independent of the number of Erase/Program cycles completion of the Program or Erase operation. On-chip that have occurred. Consequently, the system software or hardware and software data protection schemes protects hardware does not have to be modified or de-rated as is against inadvertent writes. Designed, manufactured, and necessary with alternative flash technologies, whose Erase tested for a wide spectrum of applications, the and Program times increase with accumulated Erase/Pro- SST39WF800B is offered with a guaranteed typical endur- gram cycles. ance of 100,000 cycles. Data retention is rated at greater To meet surface mount requirements, the SST39WF800B than 100 years. is offered in 48-ball TFBGA, 48-ball WFBGA, and a 48-ball The SST39WF800B is suited for applications that require XFLGA packages. See Figures 2 and 3 for pin assign- convenient and economical updating of program, configu- ments and Table 2 for pin descriptions. ration, or data memory. It significantly improves perfor- mance and reliability of all system applications while lowering power consumption. It inherently uses less energy 2009 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. S71344-02-000 12/09 MPF is a trademark of Silicon Storage Technology, Inc. 1 These specifications are subject to change without notice.8 Mbit (x16) Multi-Purpose Flash SST39WF800B Data Sheet Device Operation Sector-/Block-Erase Operation Commands, which are used to initiate the memory opera- The SST39WF800B offers both Sector-Erase and Block- tion functions of the device, are written to the device using Erase modes which allow the system to erase the device standard microprocessor write sequences. A command is on a sector-by-sector, or block-by-block, basis. written by asserting WE low while keeping CE low. The The sector architecture is based on uniform sector size of 2 address bus is latched on the falling edge of WE or CE , KWord. Initiate the Sector-Erase operation by executing a whichever occurs last. The data bus is latched on the rising six-byte command sequence with Sector-Erase command edge of WE or CE , whichever occurs first. (30H) and sector address (SA) in the last bus cycle. The Block-Erase mode is based on uniform block size of Read 32 KWord. Initiate the Block-Erase operation by executing The Read operation of the SST39WF800B is controlled by a six-byte command sequence with Block-Erase command CE and OE both have to be low for the system to obtain (50H) and block address (BA) in the last bus cycle. data from the outputs. The sector or block address is latched on the falling edge of CE is used for device selection. When CE is high, the the sixth WE pulse, while the command (30H or 50H) is chip is deselected and only standby power is consumed. latched on the rising edge of the sixth WE pulse. The internal Erase operation begins after the sixth WE pulse. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when The End-of-Erase operation can be determined using either CE or OE is high. See Figure 5. either Data Polling or Toggle Bit methods. See Figures 10 and 11 for timing waveforms. Any commands issued during Word-Program Operation the Sector- or Block-Erase operation are ignored. The SST39WF800B is programmed on a word-by-word basis. The sector where the word exists must be fully Chip-Erase Operation erased before programming. The SST39WF800B provides a Chip-Erase operation, which allows the user to erase the entire memory array to Programming is accomplished in three steps: the 1 state. This is useful when the entire device must be 1. Load the three-byte sequence for Software Data quickly erased. Protection. Initiate the Chip-Erase operation by executing a six-byte 2. Load word address and word data. During the command sequence with Chip-Erase command (10H) at Word-Program operation, the addresses are address 5555H in the last byte sequence. latched on the falling edge of either CE or WE , The Erase operation begins with the rising edge of the sixth whichever occurs last. The data is latched on the WE or CE , whichever occurs first. During the Erase rising edge of either CE or WE , whichever operation, the only valid read is Toggle Bit or Data Polling. occurs first. See Table 4 for the command sequence, Figure 9 for the 3. Initiate the internal Program operation after the timing diagram, and Figure 20 for the flowchart. Any com- rising edge of the fourth WE or CE , whichever mands issued during the Chip-Erase operation are occurs first. Once initiated, the Program operation ignored. will be completed within 40 s. See Figures 6 and 7 for WE and CE controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid reads are Data Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. 2009 Silicon Storage Technology, Inc. S71344-02-000 12/09 2