SY56017R Low Voltage 1.2V/1.8V/2.5V CML 2:1 MUX 6.4 Gbps with Equalization Features General Description 1.2V/1.8V/2.5V CML 2:1 MUX The SY56017R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 2:1 MUX with input equalization. Equalizes 9, 18, 27 inches of FR4 The SY56017R can process clock signals as fast as Guaranteed AC Performance over Temperature 4.5 GHz or data patterns up to 6.4 Gbps. and Voltage: The differential input includes Microchips unique, 3-pin - DC-to >6.4 Gbps Throughput input termination architecture that interfaces to CML - DC-to >4.5 GHz Clock Throughput differential signals, without any level-shifting or - <280 ps Propagation Delay (IN-to-Q) termination resistor networks in the signal path. The - <20 ps Input Skew differential input can also accept AC-coupled LVPECL - <80 ps Rise/Fall Times and LVDS signals. Input voltages as small as 200 mV (400 mV ) are applied before the 9, 18, or 27 FR4 Ultra-Low Jitter Design PP transmission line. For AC-coupled input interface -1 ps Cycle-to-Cycle Jitter RMS applications, an internal voltage reference is provided High-Speed CML Outputs to bias the VT pin. The outputs are CML, with extremely 2.5V 5% V , 1.2/1.8V/2.5V 5% V Power CC CCO fast rise/fall times guaranteed to be less than 80 ps. Supply Operation The SY56017R operates from a 2.5V 5% core supply Industrial Temperature Range: 40C to +85C and a 1.2V, 1.8V, or 2.5V 5% output supply and is Available In 16-Lead (3 mm x 3 mm) QFN guaranteed over the full industrial temperature range Package (40C to +85C). The SY56017R is part of Microchips high-speed, Precision Edge product line. Applications Package Type Data Distribution SY56017R SONET Clock and Data Distribution 3 mm x 3 mm QFN-16 (M) Fibre Channel Clock and Data Distribution (Top View) Gigabit Ethernet Clock And Data Distribution Markets Storage 16 15 14 13 ATE Test and Measurement /IN0 NC 1 12 Enterprise Networking Equipment VT0 11 Q 2 High-End Servers 10 VT1 3 /Q Metro Area Network Equipment IN1 9 NC 4 56 7 8 2020 Microchip Technology Inc. DS20006320A-page 1 /IN1 IN0 EQ SEL VCC GND VCCO VCCOSY56017R Functional Block Diagram IN0 0 VT0 /IN0 Q EQUALIZATION MUX /Q IN1 S 1 VT1 /IN1 EQUALIZATION EQ (3 level input) SEL (TTL/CMOS) 2DS20006320A-page 2020 Microchip Technology Inc.