ZL40215LDG1 Microchip

ZL40215 Precision 1:4 LVDS Fanout Buffer with On-Chip Input Termination Data Sheet November 2012 Ordering Information Features ZL40215LDG1 16 Pin QFN Trays Inputs/Outputs ZL40215LDF1 16 Pin QFN Tape and Reel Accepts differential or single-ended input Matte Tin LVPECL, LVDS, CML, HCSL LVCMOS Package size: 3 x 3 mm On-chip input termination resistors and biasing for o o -40 C to +85 C AC coupled inputs Four precision LVDS outputs Applications Operating frequency up to 750 MHz General purpose clock distribution Power Low jitter clock trees Options for 2.5 V or 3.3 V power supply Logic translation Clock and data signal restoration Current consumption of 62 mA Wired communications: OTN, SONET/SDH, GE, On-chip Low Drop Out (LDO) Regulator for superior 10 GE, FC and 10G FC power supply rejection Wireless communications Performance High performance micro-processor clock Ultra low additive jitter of 78 fs RMS distribution out0 p out0 n ctrl out1 p Termination and Bias vt out1 n clk p Buffer clk n out2 p out2 n out3 p out3 n Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2012, Microsemi Corporation. All Rights Reserved.ZL40215 Data Sheet Table of Contents Features . 1 Inputs/Outputs . 1 Power 1 Performance . 1 Applications . 1 1.0 Package Description 4 2.0 Pin Description . 4 3.0 Functional Description 5 3.1 Clock Inputs . 5 3.2 Clock Outputs 10 3.3 Device Additive Jitter . 13 3.4 Power Supply 14 3.4.1 Sensitivity to power supply noise . 14 3.4.2 Power supply filtering 14 3.4.3 PCB layout considerations 14 4.0 AC and DC Electrical Characteristics . 15 5.0 Performance Characterization . 17 6.0 Typical Behavior 18 7.0 Package Thermal Characteristics 19 8.0 Mechanical Drawing . 20 2 Microsemi Corporation