ZL49020DAA1

ZL49010/11, ZL49020/21, ZL49030/31 Wide Dynamic Range DTMF Receiver Data Sheet February 2007 Features Wide dynamic range (50 dB) DTMF Receiver Ordering Information Call progress (CP) detection via cadence ZL49010/11DAA 8 Pin PDIP Tubes indication ZL49020/21DAA 8 Pin PDIP Tubes 4-bit synchronous serial data output ZL49030/31DCA 18 Pin SOIC Tubes ZL49030/31DCB 18 Pin SOIC Tape & Reel Software controlled guard time for ZL490x0 ZL49030/31DDA 20 Pin SSOP Tubes Internal guard time circuitry for ZL490x1 ZL49030/31DDB 20 Pin SSOP Tape & Reel ZL49010/11DAA1 8 Pin PDIP* Tubes Powerdown option (ZL4901x & ZL4903x) ZL49020/21DAA1 8 Pin PDIP* Tubes 3.579 MHz crystal or ceramic resonator (ZL4903x ZL49030/31DCE1 18 Pin SOIC* Tubes, Bake & Drypack ZL49030/31DCF1 18 Pin SOIC* Tape & Reel, and ZL4902x) Bake & Drypack External clock input (ZL4901x) ZL49030/31DDE1 20 Pin SSOP* Tubes, Bake & Drypack ZL49030/31DDF1 20 Pin SSOP* Tubes, Bake & Drypack Guarantees non-detection of spurious tones *Pb Free Matte Tin -40C to +85C Applications Integrated telephone answering machine signal and requires external software guard time to End-to-end signalling validate the DTMF digit. The ZL490x1, with preset Fax Machines internal guard times, uses a delay steering (DStD) logic output to indicate the detection of a valid DTMF Description digit. The 4-bit DTMF binary digit can be clocked out The ZL490xx is a family of high performance DTMF synchronously at the serial data (SD) output. The SD receivers which decode all 16 tone pairs into a 4-bit pin is multiplexed with call progress detector output. In binary code. These devices incorporate an AGC for the presence of supervisory tones, the call progress wide dynamic range and are suitable for end-to-end detector circuit indicates the cadence (i.e., envelope) signalling. The ZL490x0 provides an early steering of the tone burst. The cadence information can then be (ESt) logic output to indicate the detection of a DTMF processed by an external microcontroller to identify 1 PWDN Steering Digital Circuit ESt VDD Guard Voltage or 3 Time Bias Circuit VSS High DStD Group Filter Parallel to Serial ACK Anti- Dial Code Converter Digital AGC Tone alias Converter & Latch Detector Filter Filter and Algorithm Latch Low Group Mux SD Filter 2 Oscillator OSC2 and Clock Energy OSC1 Circuit Detection (CLK) To All Chip Clocks 1. ZL49010/1 and ZL49030/1 only. 2. ZL49020/1 and ZL49030/1 only. 3. ZL490x1 only. Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2007, Zarlink Semiconductor Inc. All Rights Reserved.ZL49010/11, ZL49020/21, ZL49030/31 Data Sheet specific call progress signals. The ZL4902x and ZL4903x can be used with a crystal or a ceramic resonator without additional components. A power-down option is provided for the ZL4901x and ZL4903x. ZL49030DD/1DD ZL49010/1 ZL49020/1 ZL49030DC/1DC 20 NC 1 NC 18 NC 1 VDD 2 19 NC NC INPUT VDD INPUT VDD 1 8 1 8 2 17 INPUT NC 18 INPUT 3 VDD 16 PWDN 3 NC 17 ESt/ PWDN 4 NC ESt/ PWDN OSC2 2 7 2 7 15 DStD OSC2 4 ESt/DStD 5 16 NC ESt/DStD DStD 5 14 NC NC 15 6 NC OSC2 CLK ACK OSC1 ACK 3 6 3 6 13 OSC1 6 ACK 14 7 ACK OSC1 12 NC 7 NC 13 VSS 8 SD VSS 4 5 SD VSS 4 5 SD 11 NC 8 SD 12 9 NC NC VSS 9 10 NC 11 NC 10 NC 8 PIN PLASTIC DIP 18 PIN PLASTIC SOIC 20 PIN SSOP Figure 2 - Pin Connections Pin Description Pin Name Description 4903xDD 4903xDC 4902x 4901x 32 1 1 INPUT DTMF/CP Input. Input signal must be AC coupled via capacitor. 64 2 - OSC2 Oscillator Output. 76 3 3 OSC1 Oscillator/Clock Input. This pin can either be driven by: (CLK) 1) an external digital clock with defined input logic levels. OSC2 should be left open. 2) connecting a crystal or ceramic resonator between OSC1 and OSC2 pins. 89 4 4 V Ground. (0 V) SS 13 11 5 5 SD Serial Data/Call Progress Output. This pin serves the dual function of being the serial data output when clock pulses are applied after validation of DTMF signal, and also indicates the cadence of call progress input. As DTMF signal lies in the same frequency band as call progress signal, this pin may toggle for DTMF input. The SD pin is at logic low in powerdown state. 14 13 6 6 ACK Acknowledge Pulse Input. After ESt or DStD is high, applying a sequence of four pulses on this pin will then shift out four bits on the SD pin, representing the decoded DTMF digit. The rising edge of the first clock is used to latch the 4-bit data prior to shifting. This pin is pulled down internally. The idle state of the ACK signal should be low. 2 Zarlink Semiconductor Inc.