4Gb: x16, x32 GDDR5 SGRAM Features GDDR5 SGRAM EDW4032BABG 8 Meg x 32 I/O x 16 banks, 16 Meg x 16 I/O x 16 banks Address training: Address input monitoring via DQ Features pins V = V = 1.6V/1.55V/1.5V 3% and 1.35V 3% DD DDQ WCK2CK clock training: Phase information via EDC Data rate: 6.0 Gb/s, 7.0 Gb/s, 8.0 Gb/s pins 16 internal banks Data read and write training via read FIFO (FIFO t t Four bank groups for CCDL = 3 CK depth = 6) 8n-bit prefetch architecture: 256-bit per array read Read FIFO pattern preloaded by LDFF command or write access for x32 128-bit for x16 Direct write data load to read FIFO by WRTR com- Burst length (BL): 8 only mand Programmable CAS latency: 725 Consecutive read of read FIFO by RDTR command Programmable WRITE latency: 47 Read/write data transmission integrity secured by Programmable CRC READ latency: 23 cyclic redundancy check (CRC-8) Programmable CRC WRITE latency: 814 Read/write EDC on/off mode Programmable EDC hold pattern for CDR Low power modes Precharge: Auto option for each burst access RDQS mode on EDC pin Auto refresh and self refresh modes On-die temperature sensor with readout Refresh cycles: 16,384 cycles/32ms Automatic temperature sensor controlled self Interface: Pseudo open drain (POD-15) compatible refresh rate outputs: 40 pull-down, 60 pull-up Vendor ID, FIFO depth and density info fields for On-die termination (ODT): 60 or 120 (NOM) identification ODT and output driver strength auto calibration Mirror function with MF pin with external resistor ZQ pin: 120 Boundary scan function with SEN pin Programmable termination and driver strength off- sets 1 Options Marking Selectable external or internal V for data inputs REF Organization programmable offsets for internal V REF Density 40 Separate external V for address/command REF 128 Meg x 32 (words x bits) 32 inputs FBGA package T = 0C to +95C C 170-ball (12mm x 14mm) BG x32/x16 mode configuration set at power-up with Package environment code EDC pin Lead- and halogen-free -F Single-ended interface for data, address, and (RoHS-compliant) command Package media Quarter data rate differential clock inputs CK t, Dry pack (tray) -D CK c for address and commands Reel -R Two half data rate differential clock inputs, WCK t Timing maximum data rate and WCK c, each associated with two data bytes 6.0 Gb/s, 5.0 Gb/s -60 (DQ, DBI n, EDC) 7.0 Gb/s, 6.0 Gb/s -70 DDR data (WCK) and addressing (CK) 8.0 Gb/s, 6.0 Gb/s -80 SDR command (CK) Operating temperature Write data mask function via address bus (single/ Commercial (0C T +95C) None C double byte mask) Revision A Data bus inversion (DBI) and address bus inversion (ABI) 1. Not all options listed can be combined to Note: Input/output PLL on/off mode define an offered product. Use the part Duty cycle corrector (DCC) for data clock (WCK) catalog search on 4Gb: x16, x32 GDDR5 SGRAM Features Figure 1: Part Numbering E D W 40 32 B A BG - 70 - F - D Micron Memory Packing Media D = Dry pack (tray) Type R = Reel D = Packaged device Environment Code Product Family F = Lead-free (RoHS-compliant) W = GDDR5 SGRAM and halogen-free Density/Bank Speed 40 = 4Gb/16-bank -60 = 6.0 Gb/s -70 = 7.0 Gb/s Organization -80 = 8.0 Gb/s 32 = x32 Package Power Supply, Interface BG = 170-ball FBGA, 12mm x 14mm B = V = 1.6V/1.55V/1.5V DD Revision Note: 1. This Micron GDDR5 SGRAM is available in different speed bins. The operating range and AC timings of a faster speed bin are a superset of all slower speed bins. Therefore it is safe to use a faster bin device as a drop-in replacement of a slower bin device when operated within the supply voltage and frequency range of the slower bin device. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Microns web site: