X-On Electronics has gained recognition as a prominent supplier of MT40A1G8SA-062E:J DRAM across the USA, India, Europe, Australia, and various other global locations. MT40A1G8SA-062E:J DRAM are a product manufactured by Micron. We provide cost-effective solutions for DRAM, ensuring timely deliveries around the world.

MT40A1G8SA-062E:J Micron

MT40A1G8SA-062E:J electronic component of Micron
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Part No.MT40A1G8SA-062E:J
Manufacturer: Micron
Category: DRAM
Description: DRAM DDR4 8G 1GX8 FBGA
Datasheet: MT40A1G8SA-062E:J Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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1260 : USD 10.5867
2520 : USD 10.5747
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We are delighted to provide the MT40A1G8SA-062E:J from our DRAM category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the MT40A1G8SA-062E:J and other electronic components in the DRAM category and beyond.

8Gb: x4, x8, x16 DDR4 SDRAM Features DDR4 SDRAM MT40A2G4 MT40A1G8 MT40A512M16 1 Options Marking Features Configuration V = V = 1.2V 60mV DD DDQ 2 Gig x 4 2G4 V = 2.5V, 125mV, +250mV PP 1 Gig x 8 1G8 On-die, internal, adjustable V generation REFDQ 512 Meg x 16 512M16 1.2V pseudo open-drain I/O 78-ball FBGA package (Pb-free) x4, Refresh time of 8192-cycle at T temperature range: C x8 64ms at -40C to 85C 9mm x 13.2mm Rev. A PM 32ms at >85C to 95C 8mm x 12mm Rev. B, D, G WE 16ms at >95C to 105C 7.5mm x 11mm Rev. E, H, J, R SA 16 internal banks (x4, x8): 4 groups of 4 banks each 96-ball FBGA package (Pb-free) x16 8 internal banks (x16): 2 groups of 4 banks each 9mm x 14mm Rev. A HA 8n-bit prefetch architecture 8mm x 14mm Rev. B JY Programmable data strobe preambles 7.5mm x 13.5mm Rev. D, E, H LY Data strobe preamble training 7.5mm x 13mm Rev. J, R TB Command/Address latency (CAL) Timing cycle time Multipurpose register READ and WRITE capability 0.625ns CL = 22 (DDR4-3200) -062E Write leveling 0.682ns CL = 21 (DDR4-2933) -068 Self refresh mode 0.750ns CL = 19 (DDR4-2666) -075 Low-power auto self refresh (LPASR) 0.750ns CL = 18 (DDR4-2666) -075E Temperature controlled refresh (TCR) 0.833ns CL = 17 (DDR4-2400) -083 Fine granularity refresh 0.833ns CL = 16 (DDR4-2400) -083E Self refresh abort 0.937ns CL = 15 (DDR4-2133) -093E Maximum power saving 1.071ns CL = 13 (DDR4-1866) -107E Output driver calibration Operating temperature Nominal, park, and dynamic on-die termination Commercial (0 T 95C) None C (ODT) Industrial (40 T 95C) IT C Data bus inversion (DBI) for data bus Automotive (40 T 105C) AT C Command/Address (CA) parity Revision :A, :B, :D, :E, Databus write cyclic redundancy check (CRC) :G, :H, :J, :R Per-DRAM addressability 1. Not all options listed can be combined to Note: Connectivity test define an offered product. Use the part JEDEC JESD-79-4 compliant catalog search on 8Gb: x4, x8, x16 DDR4 SDRAM Features Table 1: Key Timing Parameters (Continued) 1 t t t Speed Grade Data Rate (MT/s) Target CL-nRCD-nRP AA (ns) RCD (ns) RP (ns) -075E 2666 18-18-18 13.50 13.50 13.50 -075 2666 19-19-19 14.25 (13.75) 14.25 (13.75) 14.25 (13.75) -083E 2400 16-16-16 13.32 13.32 13.32 -083 2400 17-17-17 14.16 (13.75) 14.16 (13.75) 14.16 (13.75) -093E 2133 15-15-15 14.06 (13.50) 14.06 (13.50) 14.06 (13.50) -093 2133 16-16-16 15.00 15.00 15.00 -107E 1866 13-13-13 13.92 (13.50) 13.92 (13.50) 13.92 (13.50) Note: 1. Refer to the Speed Bin Tables for additional details. Table 2: Addressing Parameter 2048 Meg x 4 1024 Meg x 8 512 Meg x 16 Number of bank groups 4 4 2 Bank group address BG 1:0 BG 1:0 BG0 Bank count per group 4 4 4 Bank address in bank group BA 1:0 BA 1:0 BA 1:0 Row addressing 128K (A 16:0 ) 64K (A 15:0 ) 64K (A 15:0 ) Column addressing 1K (A 9:0 ) 1K (A 9:0 ) 1K (A 9:0 ) 1 Page size 512B 1KB 2KB Note: 1. Page size is per bank, calculated as follows: COLBITS Page size = 2 ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits. CCMTD-1725822587-9875 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 8gb ddr4 dram.pdf - Rev. S 12/2020 EN 2015 Micron Technology, Inc. All rights reserved.

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:
Elpida Memory
ELPIDA MEMORY INC
IE6
MI9
MICRON SEMICONDUCTOR
Micron Tech
MICRON TECHNOLOGY
Micron Technology Inc
Micron Technology Inc.
NU9
Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC. (VA)

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