MT46H32M32LFB5-5 AIT:B TR

1Gb: x16, x32 Automotive LPDDR SDRAM Features Automotive LPDDR SDRAM MT46H64M16LF 16 Meg x 16 x 4 banks MT46H32M32LF 8 Meg x 32 x 4 banks MT46H32M32LG 8 Meg x 32 x 4 banks Options Marking Features V /V DD DDQ V /V = 1.701.95V DD DDQ 1.8V/1.8V H Bidirectional data strobe per byte of data (DQS) Configuration Internal, pipelined double data rate (DDR) 64 Meg x 16 (16 Meg x 16 x 4 64M16 architecture two data accesses per clock cycle banks) 32 Meg x 32 (8 Meg x 32 x 4 banks) 32M32 Differential clock inputs (CK and CK ) Addressing Commands entered on each positive CK edge JEDEC-standard LF DQS edge-aligned with data for READs center- JEDEC reduced page size LG aligned with data for WRITEs Plasticgree package 4 internal banks for concurrent operation 1 60-ball VFBGA (8mm x 9mm) BF 2 Data masks (DM) for masking write data one mask 90-ball VFBGA (8mm x 13mm) B5 per byte PoP (plasticgree package) 2 Programmable burst lengths (BL): 2, 4, 8, or 16 168-ball WFBGA (12mm x 12mm) MA Timing cycle time Concurrent auto precharge option is supported 5ns CL = 3 (200 MHz) -5 Auto refresh and self refresh modes 5.4ns CL = 3 (185 MHz) -54 1.8V LVCMOS-compatible inputs 6ns CL = 3 (166 MHz) -6 Temperature-compensated self refresh (TCSR) 7.5ns CL = 3 (133 MHz) -75 Partial-array self refresh (PASR) Power Deep power-down (DPD) Standard I /I None DD2 DD6 Product grade Status read register (SRR) Automotive (package-level A Selectable output drive strength (DS) burn-in) Clock stop capability Operating temperature range 64ms refresh, 32ms for automotive temperature Commercial (0 to +70C) None Industrial (40C to +85C) IT 3 Table 1: Key Timing Parameters (CL = 3) Automotive (40C to +105C) AT Design revision :B Speed Grade Clock Rate Access Time 1. Only available for x16 configuration. -5 200 MHz 5.0ns Notes: 2. Only available for x32 configuration. -54 185 MHz 5.0ns 3. Contact factory for availability. -6 166 MHz 5.0ns -75 133 MHz 6.0ns 09005aef84812cd1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 t68m auto lpddr.pdf - Rev. F 05/18 EN 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.1Gb: x16, x32 Automotive LPDDR SDRAM Features Table 2: Configuration Addressing Reduced Page Size Architecture 64 Meg x 16 32 Meg x 32 32 Meg x 32 Configuration 16 Meg x 16 x 4 banks 8 Meg x 32 x 4 banks 8 Meg x 32 x 4 banks Refresh count 8K 8K 8K Row addressing 16K A 13:0 8K A 12:0 16K A 13:0 Column addressing 1K A 9:0 1K A 9:0 512 A 8:0 Figure 1: 1Gb Mobile LPDDR Part Numbering MT 46 H 64M16 LF BF -6 A IT :B Micron Technology Design Revision :B = Second generation Product Family 46 = Mobile LPDDR Operating Temperature Blank = Commercial (0C to +70C) Operating Voltage IT = Industrial (40C to +85C) H = 1.8/1.8V AT = Automotive (40C to +105C) Product Grade Configuration 64 Meg x 16 A = Automotive (package-level burn-in) 32 Meg x 32 Power Blank = Standard I /I Addressing DD2 DD6 LF = JEDEC-standard Cycle Time (CL = 3) LG = JEDEC reduced page size t -5 = 5ns CK t -54 = 5.4ns CK Package Codes t -6 = 6ns CK BF = 60-ball (8mm x 9mm) VFBGA, green t -75 = 7.5ns CK B5 = 90-ball (8mm x 13mm) VFBGA, green MA = 168-ball (12mm x 12mm) WFBGA, green FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Microns FBGA part marking decoder is available at www.micron.com/decoder. 09005aef84812cd1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 t68m auto lpddr.pdf - Rev. F 05/18 EN 2011 Micron Technology, Inc. All rights reserved.