MT47H32M16HR-25EIT:GTR Micron

512Mb: x4, x8, x16 DDR2 SDRAM Features DDR2 SDRAM MT47H128M4 32 Meg x 4 x 4 banks MT47H64M8 16 Meg x 8 x 4 banks MT47H32M16 8 Meg x 16 x 4 banks 1 Options Marking Features Configuration V = 1.8V 0.1V, V = 1.8V 0.1V DD DDQ 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4 JEDEC-standard 1.8V I/O (SSTL 18-compatible) 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 Differential data strobe (DQS, DQS ) option 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 FBGA package (Pb-free) x16 4n-bit prefetch architecture 84-ball FBGA (8mm x 12.5mm) Rev. F, G HR Duplicate output strobe (RDQS) option for x8 FBGA package (Pb-free) x4, x8 DLL to align DQ and DQS transitions with CK 60-ball FBGA (8mm x 10mm) Rev. F, G CF 4 internal banks for concurrent operation FBGA package (lead solder) x16 Programmable CAS latency (CL) 84-ball FBGA (8mm x 12.5mm) Rev. F, G HW Posted CAS additive latency (AL) FBGA package (lead solder) x4, x8 t 60-ball FBGA (8mm x 10mm) Rev. F, G JN WRITE latency = READ latency - 1 CK Timing cycle time Selectable burst lengths: 4 or 8 1.875ns CL = 7 (DDR2-1066) -187E Adjustable data-output drive strength 2.5ns CL = 5 (DDR2-800) -25E 64ms, 8192-cycle refresh 2.5ns CL = 6 (DDR2-800) -25 On-die termination (ODT) 3.0ns CL = 4 (DDR2-667) -3E Industrial temperature (IT) option 3.0ns CL = 5 (DDR2-667) -3 3.75ns CL = 4 (DDR2-533) -37E Automotive temperature (AT) option Self refresh RoHS-compliant Standard None Supports JEDEC clock jitter specification Low-power L Operating temperature Commercial (0C T +85C) None C Industrial (40C T +95C IT C 40C T +85C) A Automotive (40C T , T +105C) AT C A Revision :F/:G 1. Not all options listed can be combined to Note: define an offered product. Use the Part Catalog Search on www.micron.com for product offerings and availability. PDF: 09005aef82f1e6e2 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 512MbDDR2.pdf - Rev. T 2/12 EN 2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.512Mb: x4, x8, x16 DDR2 SDRAM Features Table 1: Key Timing Parameters Data Rate (MT/s) t Speed Grade CL = 3 CL = 4 CL = 5 CL = 6 CL = 7 RC (ns) -187E 400 533 800 800 1066 54 -25E 400 533 800 800 n/a 55 -25 400 533 667 800 n/a 55 -3E 400 667 667 n/a n/a 54 -3 400 533 667 n/a n/a 55 -37E 400 533 n/a n/a n/a 55 Table 2: Addressing Parameter 128 Meg x 4 64 Meg x 8 32 Meg x 16 Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks Refresh count 8K 8K 8K Row address A 13:0 (16K) A 13:0 (16K) A 12:0 (8K) Bank address BA 1:0 (4) BA 1:0 (4) BA 1:0 (4) Column address A 11, 9:0 (2K) A 9:0 (1K) A 9:0 (1K) Figure 1: 512Mb DDR2 Part Numbers Example Part Number: MT47H128M4HR-25E :G - : MT47H Configuration Package Speed Revision :F/:G Revision Configuration 128 Meg x 4 128M4 64 Meg x 8 64M8 L Low power 32 Meg x 16 32M16 IT Industrial temperature AT Automotive temperature Package Speed Grade Pb-free t -37E CK = 3.75ns, CL = 4 84-ball 8mm x 12.5mm FBGA HR t -3 CK = 3ns, CL = 5 60-ball 8mm x 10mm FBGA CF t -3E CK = 3ns, CL = 4 Lead Solder t 84-ball 8mm x 12.5mm FBGA -25 CK = 2.5ns, CL = 6 HW t 60-ball 8mm x 10mm FBGA -25E CK = 2.5ns, CL = 5 JN t -187E CK = 1.875ns, CL = 7 Note: 1. Not all speeds and configurations are available in all packages. PDF: 09005aef82f1e6e2 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 512MbDDR2.pdf - Rev. T 2/12 EN 2004 Micron Technology, Inc. All rights reserved.