MT48LC4M16A2P-7E

64Mb: x4, x8, x16 SDRAM Features SDR SDRAM MT48LC16M4A2 4 Meg x 4 x 4 Banks MT48LC8M8A2 2 Meg x 8 x 4 Banks MT48LC4M16A2 1 Meg x 16 x 4 Banks Options Marking Features t WR = 2 CLK A2 PC100- and PC133-compliant 1 Plastic package OCPL Fully synchronous all signals registered on positive 54-pin TSOP II (400 mil) TG edge of system clock 54-pin TSOP II (400 mil) Pb-free P Internal, pipelined operation column address can 54-ball VFBGA (x16 only) (8mm x F4 be changed every clock cycle 8mm) Internal banks for hiding row access/precharge 2 54-ball VFBGA (x16 only) (8mm x B4 Programmable burst lengths: 1, 2, 4, 8, or full page 8mm) Auto precharge, includes concurrent auto precharge Timing cycle time and auto refresh modes 3 6ns CL = 3 (x16 only) -6 Self refresh modes: Standard and low power 6ns CL = 3 -6A (not available on AT devices) 3 7.5ns CL = 3 (PC133) -75 Auto Refresh 7.5ns CL = 2 (PC133) -7E 64ms, 4096-cycle refresh Self refresh (commercial and industrial) Standard None 16ms, 4096-cycle refresh 3 Low power L (automotive) Operating temperature range LVTTL-compatible inputs and outputs Commercial (0C to +70C) None Single 3.3V 0.3V power supply Industrial (40C to +85C) IT 2 Automotive (40C to +105C) AT Options Marking Revision :G, :J Configuration 3 16 Meg x 4 (4 Meg x 4 x 4 banks) 16M4 1. Off-center parting line. Notes: 8 Meg x 8 (2 Meg x 8 x 4 banks) 8M8 2. Contact Micron for availability. 4 Meg x 16 (1 Meg x 16 x 4 banks) 4M16 3. Only available on Revision G. t Write recovery ( WR) Table 1: Key Timing Parameters CL = CAS (READ) latency Clock t t t t Speed Grade Frequency (MHz) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) -6 167 3-3-3 18 18 18 -6A 167 3-3-3 18 18 18 -75 133 3-3-3 20 20 20 -7E 133 2-2-2 15 15 15 PDF: 09005aef80725c0b Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 64mb x4x8x16 sdram.pdf - Rev. R 10/12 EN 1999 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.64Mb: x4, x8, x16 SDRAM Features Table 2: Address Table Parameter 16 Meg x 4 8 Meg x 8 4 Meg x 16 Configuration 4 Meg x 4 x 4 banks 2 Meg x 8 x 4 banks 1 Meg x 16 x 4 banks Refresh count 4K 4K 4K Row addressing 4K A 11:0 4K A 11:0 4K A 11:0 Bank addressing 4 BA 1:0 4 BA 1:0 4 BA 1:0 Column addressing 1K A 9:0 512 A 8:0 256 A 7:0 Table 3: 64Mb SDR Part Numbering Part Numbers Architecture Package MT48LC16M4A2TG 16 Meg x 4 54-pin TSOP II MT48LC16M4A2P 16 Meg x 4 54-pin TSOP II MT48LC8M8A2TG 8 Meg x 8 54-pin TSOP II MT48LC8M8A2P 8 Meg x 8 54-pin TSOP II MT48LC4M16A2TG 4 Meg x 16 54-pin TSOP II MT48LC4M16A2P 4 Meg x 16 54-pin TSOP II 1 MT48LC4M16A2B4 4 Meg x 16 54-ball VFBGA 1 MT48LC4M16A2F4 4 Meg x 16 54-ball VFBGA Note: 1. FBGA Device Decoder: www.micron.com/decoder. PDF: 09005aef80725c0b Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 64mb x4x8x16 sdram.pdf - Rev. R 10/12 EN 1999 Micron Technology, Inc. All rights reserved.