74ALVC02BQ,115

74ALVC02 Quad 2-input NOR gate Rev. 5 27 July 2021 Product data sheet 1. General description The 74ALVC02 is a quad 2-input NOR gate. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. 2. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF R = 0 ) Multiple package options Specified from -40 C to +85 CNexperia 74ALVC02 Quad 2-input NOR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC02D -40 C to +85 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74ALVC02PW -40 C to +85 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74ALVC02BQ -40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mm 4. Functional diagram 2 2 1A 1 1 1 1Y 3 3 1B 5 5 2A 1 4 2Y 4 6 6 2B 8 3A 8 10 3Y 1 10 9 3B 9 A 11 4A 11 13 4Y Y 1 12 4B 13 12 B mna216 001aah084 mna215 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74ALVC02 1 14 1Y V CC 74ALVC02 1A 2 13 4Y 1Y 1 14 V 1B 3 12 4B CC 1A 2 13 4Y 2Y 4 11 4A 1B 3 12 4B 2Y 4 11 4A 2A 5 10 3Y 2A 5 10 3Y 6 9 2B 3B 2B 6 9 3B GND 7 8 3A GND 7 8 3A aaa-027353 aaa-027354 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 74ALVC02 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 27 July 2021 2 / 13