74ALVC574PW,112

74ALVC574 Octal D-type flip-flop positive edge-trigger 3-state Rev. 3 30 April 2021 Product data sheet 1. General description The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74ALVC574 is functionally identical to the 74ALVC374, but has a different pin arrangement. 2. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 VNexperia 74ALVC574 Octal D-type flip-flop positive edge-trigger 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC574D -40 C to +85 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74ALVC574PW -40 C to +85 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74ALVC574BQ -40 C to +85 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals body 2.5 4.5 0.85 mm 4. Functional diagram 11 C1 1 EN 11 2 19 CP 1D 2 19 D0 Q0 3 18 3 18 D1 Q1 4 17 4 17 D2 Q2 5 16 5 16 D3 Q3 6 15 6 15 D4 Q4 7 14 D5 7 14 Q5 8 13 D6 Q6 8 13 9 12 D7 Q7 9 12 OE 1 mna798 mna446 Fig. 1. Logic symbol Fig. 2. IEC logic symbol D0 Q0 2 19 3 D1 Q1 18 4 D2 Q2 17 5 D3 FF1 Q3 16 3-STATE to 6 D4 OUTPUTS Q4 15 FF8 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 11 CP 1 OE mna800 Fig. 3. Functional diagram 74ALVC574 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 30 April 2021 2 / 15