Product Information

74ALVCH16825DGGS

74ALVCH16825DGGS electronic component of Nexperia

Datasheet
Buffers & Line Drivers 18-Bit Buffer/ Driver, 3-State
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - WHS 1

MOQ : 875
Multiples : 1
875 : USD 0.9914
1000 : USD 0.841
2500 : USD 0.8224
N/A

Obsolete
0 - WHS 2

MOQ : 1
Multiples : 1
1 : USD 2.7853
10 : USD 2.0053
25 : USD 1.8918
105 : USD 1.6269
280 : USD 1.4916
525 : USD 1.2854
1015 : USD 1.2078
N/A

Obsolete

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RoHS - XON
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Additional Infomation About Product

74ALVCH16825 18-bit buffer/driver 3-state Rev. 3 6 April 2018 Product data sheet 1 General description The 74ALVCH16825 is an 18bit non-inverting buffer/driver with 3-state outputs for bus-oriented applications. The 74ALVCH16825 consists of two 9-bit sections with separate output enable signals. For either 9-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be LOW for corresponding nYn outputs to be active. If either output enable input is HIGH, the outputs of that 9-buffer section are in the high impedance state. The 74ALVCH16825 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2 Features and benefits Wide supply voltage range of 1.2V to 3.6V CMOS low power consumption MultiByte flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimum noise and ground bounce CC Direct interface with TTL levels (2.7 V to 3.6 V) Bus hold on data inputs Output drive capability 50 transmission lines at 85 C Current drive 24 mA at 3.0 V Complies with JEDEC standards: JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V CDM JESD22-C101E exceeds 1000 V 3 Ordering information Table 1.Ordering information Type number Package Temperature Name Description Version range 74ALVCH16825DGG 40 C to +85 C TSSOP56 plastic thin shrink small outline package 56 leads SOT364-1 body width 6.1 mmNexperia 74ALVCH16825 18-bit buffer/driver 3-state 4 Functional diagram 1 & 1OE1 EN1 56 1OE2 28 2OE1 & EN2 29 55 54 52 51 49 48 47 45 44 2OE2 55 2 1A0 1 1 1Y0 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 54 3 1A1 1Y1 1 1OE1 52 5 1A2 1Y2 51 6 56 1OE2 1A3 1Y3 49 8 1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1A4 1Y4 48 9 1A5 1Y5 47 10 1A6 1Y6 2 3 5 6 8 9 10 12 13 45 12 1A7 1Y7 44 13 1A8 1Y8 41 16 41 40 38 37 36 34 33 31 30 1 2 2A0 2Y0 40 17 2A1 2Y1 38 19 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A2 2Y2 37 20 2A3 2Y3 28 2OE1 36 21 2A4 2Y4 29 2OE2 34 23 2A5 2Y5 33 24 2Y0 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 2A6 2Y6 31 26 2A7 2Y7 30 27 15 17 19 20 21 23 24 26 27 2A8 2Y8 aaa-028390 aaa-028391 Figure 1.Logic symbol Figure 2.IEC logic symbol nA0 nA1 nA2 nA3 nA4 nA5 nA6 nA7 nA8 nOE1 nOE2 nY0 nY1 nY2 nY3 nY4 nY5 nY6 nY7 nY8 aaa-028392 Figure 3.Logic diagram V CC data input to internal circuit 001aal733 Figure 4.Bus hold circuit 74ALVCH16825 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. Product data sheet Rev. 3 6 April 2018 2 / 14

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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