74AUP1G04GW-Q100H Nexperia

74AUP1G04-Q100 Low-power inverter Rev. 2 30 April 2021 Product data sheet 1. General description The 74AUP1G04-Q100 provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range CC from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V HBM JESD22-A114F Class 3A. Exceeds 5000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78B Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF 3. Ordering information Table 1. Ordering information Type number Package Temperature Name Description Version range 74AUP1G04GV-Q100 -40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 74AUP1G04GW-Q100 -40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mmNexperia 74AUP1G04-Q100 Low-power inverter 4. Marking Table 2. Marking Type number Marking code 1 74AUP1G04GV-Q100 p04 74AUP1G04GW-Q100 pC 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram A Y 1 A Y mna108 mna109 mna110 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1G04-Q100 n.c. 1 5 V CC A 2 GND 3 4 Y aaa-009631 Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A) 6.2. Pin description Table 3. Pin description Symbol Pin Description n.c. 1 not connected A 2 data input GND 3 ground (0 V) Y 4 data output V 5 supply voltage CC 74AUP1G04 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 2 30 April 2021 2 / 14