Product Information

74AUP1G32GW-Q100H

74AUP1G32GW-Q100H electronic component of Nexperia

Datasheet
Logic Gates Low-power 2-input OR-gate
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

3000: USD 0.0738 ea
Line Total: USD 221.4

14550 - Global Stock
Ships to you between
Fri. 17 May to Thu. 23 May
MOQ: 3000  Multiples: 3000
Pack Size: 3000

 More Buying Options & Price Grid(s)

Availability Price Quantity
14550 - WHS 1


Ships to you between Fri. 17 May to Thu. 23 May

MOQ : 3000
Multiples : 3000
3000 : USD 0.0738
6000 : USD 0.0725
12000 : USD 0.0713
18000 : USD 0.0701
24000 : USD 0.0688

2323 - WHS 2


Ships to you between
Fri. 24 May to Wed. 29 May

MOQ : 5
Multiples : 5
5 : USD 0.3233
50 : USD 0.2839
150 : USD 0.2671
500 : USD 0.246
3000 : USD 0.2365
6000 : USD 0.231

55351 - WHS 3


Ships to you between Thu. 23 May to Mon. 27 May

MOQ : 1
Multiples : 1
1 : USD 0.4761
10 : USD 0.3588
100 : USD 0.2231
1000 : USD 0.1208
3000 : USD 0.0954
9000 : USD 0.0874
24000 : USD 0.084
45000 : USD 0.084
99000 : USD 0.0805

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Product
Logic Function
Logic Family
Number of Gates
Number of Input Lines
Number of Output Lines
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Operating Temperature Range
Output Current
Output Voltage
Brand
Pd - Power Dissipation
Factory Pack Quantity :
Cnhts
Hts Code
Mxhts
Product Type
Subcategory
Taric
LoadingGif

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Additional Infomation About Product

74AUP1G32-Q100 Low-power 2-input OR-gate Rev. 4 23 April 2021 Product data sheet 1. General description The 74AUP1G32-Q100 provides the single 2-input OR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range CC from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V HBM JESD22-A114F Class 3A. Exceeds 5000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G32GW-Q100 -40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74AUP1G32GM-Q100 -40 C to +125 C XSON6 plastic extremely thin small outline package SOT886 no leads 6 terminals body 1 1.45 0.5 mmNexperia 74AUP1G32-Q100 Low-power 2-input OR-gate 4. Marking Table 2. Marking Type number Marking code 1 74AUP1G32GW-Q100 pG 74AUP1G32GM-Q100 pG 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram B 1 B 1 1 Y 4 4 Y 2 A 2 A mna164 mna165 mna166 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1G32 74AUP1G32 B 1 6 V CC B 1 5 V CC A 2 5 n.c. A 2 GND 3 4 Y GND 3 4 Y 001aaf029 Transparent top view 001aaf028 Fig. 4. Pin configuration SOT353-1 (TSSOP5) Fig. 5. Pin configuration SOT886 (XSON6) 6.2. Pin description Table 3. Pin description Symbol Pin Description TSSOP5 XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected V 5 6 supply voltage CC 74AUP1G32 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 23 April 2021 2 / 14

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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