Product Information

74AUP2G00GM,125

74AUP2G00GM,125 electronic component of Nexperia

Datasheet
Logic Gates 1.8V DUAL LP DUAL

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - Global Stock

MOQ : 4000
Multiples : 4000
4000 : USD 0.2606
8000 : USD 0.2484
12000 : USD 0.2466
16000 : USD 0.2448
20000 : USD 0.2429
24000 : USD 0.241
40000 : USD 0.2392
60000 : USD 0.2374
100000 : USD 0.2356
N/A

Obsolete
0 - Global Stock

MOQ : 1
Multiples : 1
1 : USD 0.3218
5 : USD 0.3159
50 : USD 0.2925
250 : USD 0.2516
1000 : USD 0.2305
2500 : USD 0.2258
N/A

Obsolete
0 - Global Stock

MOQ : 1
Multiples : 1
1 : USD 0.9991
10 : USD 0.7073
100 : USD 0.1414
1000 : USD 0.1142
4000 : USD 0.104
8000 : USD 0.099
24000 : USD 0.0951
48000 : USD 0.0926
100000 : USD 0.0901
N/A

Obsolete
     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Logic Family
Number of Gates
Number of Input Lines
Number of Output Lines
High Level Output Current
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Brand
Factory Pack Quantity :
Function
Height
Length
Width
Logic Type
Cnhts
Hts Code
Mxhts
Operating Supply Voltage
Product Type
Subcategory
Taric
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74AUP2G00 Low-power dual 2-input NAND gate Rev. 10 3 July 2017 Product data sheet 1 General description The 74AUP2G00 provides dual 2-input NAND function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2 Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5 000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1 000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 CNexperia 74AUP2G00 Low-power dual 2-input NAND gate 3 Ordering information Table 1.Ordering information Type number Package Temperature Name Description Version range 74AUP2G00DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 leads SOT765-1 body width 2.3 mm 74AUP2G00GT -40 C to +125 C XSON8 plastic extremely thin small outline package no leads SOT833-1 8 terminals body 1 x 1.95 x 0.5 mm 74AUP2G00GF -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1089 8 terminals body 1.35 x 1 x 0.5 mm 74AUP2G00GM -40 C to +125 C XQFN8 plastic, extremely thin quad flat package no leads SOT902-2 8 terminals body 1.6 x 1.6 x 0.5 mm 74AUP2G00GN -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1116 8 terminals body 1.2 x 1.0 x 0.35 mm 74AUP2G00GS -40 C to +125 C XSON8 extremely thin small outline package no leads SOT1203 8 terminals body 1.35 x 1.0 x 0.35 mm 74AUP2G00GX -40 C to +125 C X2SON8 plastic thermal enhanced extremely thin SOT1233 small outline package no leads 8 terminals body 1.35 x 0.8 x 0.35 mm 4 Marking Table 2.Marking codes 1 Type number Marking code 74AUP2G00DC p00 74AUP2G00GT p00 74AUP2G00GF pA 74AUP2G00GM p00 74AUP2G00GN pA 74AUP2G00GS pA 74AUP2G00GX pA 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74AUP2G00 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 10 3 July 2017 2 / 22

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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