74HC138D,652

74HC138 74HCT138 3-to-8 line decoder/demultiplexer inverting Rev. 9 13 August 2021 Product data sheet 1. General description The 74HC138 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four 138 ICs and one inverter. The 138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding Active LOW mutually exclusive outputs Input levels: For 74HC138: CMOS level For 74HCT138: TTL level Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC138D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT138D 74HC138PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74HCT138PW 74HC138BQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals 74HCT138BQ body 2.5 3.5 0.85 mmNexperia 74HC138 74HCT138 3-to-8 line decoder/demultiplexer inverting 4. Functional diagram Y0 15 A0 Y1 1 14 2 A1 Y2 13 3 A2 Y3 12 3-to-8 ENABLE 1 A0 Y0 15 Y4 11 DECODER EXITING A1 Y1 14 2 Y5 10 3 A2 Y2 13 Y6 9 Y3 12 7 Y7 11 E1 Y4 4 4 E1 10 Y5 E2 5 5 E2 Y6 9 E3 6 6 E3 Y7 7 mna370 mna372 Fig. 1. Logic symbol Fig. 2. Functional diagram Y7 A2 Y6 A1 Y5 A0 Y4 E1 Y3 E2 Y2 E3 Y1 Y0 001aae059 Fig. 3. Logic diagram 74HC HCT138 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 9 13 August 2021 2 / 15