74HC280D,652

74HC280 74HCT280 9-bit odd/even parity generator/checker Rev. 4 16 August 2021 Product data sheet 1. General description The 74HC280 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Word-length easily expanded by cascading Generates either odd or even parity for nine data bits Wide supply voltage range from 2.0 to 6.0 V Input levels: For 74HC280: CMOS level For 74HCT280: TTL level CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Temperature Name Description Version range 74HC280D -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT280D 74HCT280PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mmNexperia 74HC280 74HCT280 9-bit odd/even parity generator/checker 4. Functional diagram 8 I0 9 I1 10 I2 PE 5 11 I3 I4 12 13 I5 PO 6 1 I6 2 I7 4 I8 aaa-024423 Fig. 1. Logic symbol I0 I1 I2 PE I3 I4 I5 PO I6 I7 I8 aaa-024424 Fig. 2. Logic diagram 74HC HCT280 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 16 August 2021 2 / 13