74HC368D,652 Nexperia

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT368 Hex buffer/line driver 3-state inverting December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Hex buffer/line driver 3-state inverting 74HC/HCT368 FEATURES The 74HC/HCT368 are hex inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are Inverting outputs controlled by the output enable inputs (1OE, 2OE). Output capability: bus driver A HIGH on nOE causes the outputs to assume a high I category: MSI CC impedance OFF-state. The 368 is identical to the 367 but has inverting outputs. GENERAL DESCRIPTION The 74HC/HCT368 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay nA to nYC = 15 pF V =5V 9 11 ns PHL PLH L CC C input capacitance 3.5 3.5 pF I C power dissipation capacitance per buffer notes 1 and 2 30 30 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2