74HC3G34DP,125 Nexperia

74HC3G34 74HCT3G34 Triple buffer gate Rev. 7 11 June 2018 Product data sheet 1 General description The 74HC3G34 74HCT3G34 is a triple buffer. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2 Features and benefits Wide supply voltage range from 2.0 V to 6.0 V Input levels: For 74HC3G34: CMOS level For 74HCT3G34: TTL level Complies with JEDEC standard no. 7 A Symmetrical output impedance High noise immunity Low-power dissipation Balanced propagation delays Multiple package options ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and -40 C to +125 C 3 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74HC3G34DP -40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm 74HCT3G34DP 74HC3G34DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74HCT3G34DCNexperia 74HC3G34 74HCT3G34 Triple buffer gate 4 Marking Table 2.Marking 1 Type number Marking code 74HC3G34DP H34 74HCT3G34DP T34 74HC3G34DC P34 74HCT3G34DC U34 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5 Functional diagram 1 1 7 1 1A 1Y 7 1 3 5 2 3Y 3A 6 3 2A 2Y 5 1 6 2 mna744 mna745 Figure 1. Logic symbol Figure 2. IEC logic symbol 6 Pinning information 6.1 Pinning 74HC3G34 74HCT3G34 1A 1 8 V CC 3Y 2 7 1Y 3 6 2A 3A 4 5 GND 2Y 001aae470 Figure 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74HC HCT3G34 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. Product data sheet Rev. 7 11 June 2018 2 / 13