74HC4515 4-to-16 line decoder/demultiplexer with input latches inverting Rev. 3 2 July 2018 Product data sheet 1 General description The 74HC4515 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3) with latches, a latch enable input (LE), an enable input (E) and 16 inverting outputs (Q0, to Q15). When LE is HIGH, the selected output is determined by the data on An. When LE goes LOW, the last data present at An are stored in the latches and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the latch, is LOW. When E is HIGH, all outputs are HIGH. The enable input E does not affect the state of the latch. When the device is used as a demultiplexer, E is the data input and A0 to A3 are the address inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2 Features and benefits Inverting outputs CMOS input levels 16-line demultiplexing capability Decodes 4 binary-coded inputs into 16 mutually-exclusive outputs Complies with JEDEC standard no. 7 A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and -40 C to +125 C 3 Applications Digital multiplexing Address decoding Hexadecimal/BCD decoding 4 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74HC4515D 40 C to +125 C SO24 plastic small outline package 24 leads SOT137-1 body width 7.5 mmNexperia 74HC4515 4-to-16 line decoder/demultiplexer with input latches inverting 5 Functional diagram DX X/Y Q0 11 0 11 0 11 Q1 9 1 9 1 9 Q2 10 2 10 2 10 1 LE Q3 8 3 8 3 8 Q4 7 1 C4 4 7 1 C9 4 7 2 A0 Q5 6 5 6 5 6 Q6 5 2 0 6 5 2 9D, 1 6 5 3 A1 Q7 4 3 7 4 3 9D, 2 7 4 0 4D, G 15 Q8 18 21 8 18 21 9D, 4 8 18 21 A2 Q9 17 22 3 9 17 22 9D, 8 9 17 Q10 20 10 20 10 20 22 A3 Q11 19 23 11 19 23 EN 11 19 Q12 14 12 14 12 14 23 E Q13 13 13 13 13 13 Q14 16 14 16 14 16 Q15 15 15 15 15 15 aaa-028693 aaa-028694 Figure 1.Logic symbol Figure 2.IEC logic symbol 2 3 21 22 A0 A1 A2 A3 LE 1 LATCHES E 23 DECODER Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 11 9 10 8 7 6 5 4 18 17 20 19 14 13 16 15 aaa-028695 Figure 3.Functional diagram 74HC4515 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. Product data sheet Rev. 3 2 July 2018 2 / 14