74HC4520D,118

74HC4520 74HCT4520 Dual 4-bit synchronous binary counter Rev. 6 9 October 2020 Product data sheet 1. General description The 74HC4520 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on the LOW-to-HIGH transition of nCP0 when nCP1 is HIGH. It also advances on the HIGH-to-LOW transition of nCP1 when nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter. The other clock input may be used as a clock enable input. A HIGH on nMR, resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC4520: CMOS level For 74HCT4520: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and -40 C to +125 C 3. Applications Multistage synchronous counting Multistage asynchronous counting Frequency dividers 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC4520D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74HCT4520D 74HC4520PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package SOT403-1 16 leads body width 4.4 mmNexperia 74HC4520 74HCT4520 Dual 4-bit synchronous binary counter 5. Functional diagram 1Q0 3 1 1CP0 1Q1 4 2 1CP1 1Q2 5 1Q3 6 7 1MR 2Q0 11 9 2CP0 2Q1 12 10 2CP1 2Q2 13 2Q3 14 15 2MR 001aae698 Fig. 1. Functional diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 nCP0 nCP1 nMR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 nQ0 nQ1 nQ2 nQ 3 001aae707 Fig. 2. Timing diagram nQ0 nQ1 nQ2 nQ3 Q Q Q Q FF1 FF2 FF3 FF4 nCP1 CP CP CP CP Q Q Q Q RD RD RD RD nCP0 nMR aaa-015608 Fig. 3. Logic diagram for one counter 74HC HCT4520 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 9 October 2020 2 / 14