Product Information

74HC540DB,118

74HC540DB,118 electronic component of Nexperia

Datasheet
Buffers & Line Drivers OCTAL BUF/DRV INV 3S
Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

2000: USD 0.5608 ea
Line Total: USD 1121.6

970 - Global Stock
Ships to you between
Mon. 13 May to Fri. 17 May
MOQ: 2000  Multiples: 1000
Pack Size: 1000

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970 - WHS 1


Ships to you between Mon. 13 May to Fri. 17 May

MOQ : 2000
Multiples : 1000

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74HC540DB,118
Nexperia

2000 : USD 0.5608

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Input Lines
Number of Output Lines
Polarity
Supply Voltage - Max
Supply Voltage - Min
High Level Output Current
Low Level Output Current
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Output Type
Brand
Logic Family
Logic Type
Number Of Channels Per Chip
Propagation Delay Time
Factory Pack Quantity :
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Additional Infomation About Product

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT540 Octal buffer/line driver 3-state inverting December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Octal buffer/line driver 3-state 74HC/HCT540 inverting FEATURES The 74HC/HCT540 are octal inverting buffer/line drivers with 3-state outputs. The 3-state outputs are controlled by Inverting outputs the output enable inputs OE and OE . 1 2 Output capability: bus driver A HIGH on OE causes the outputs to assume a high n impedance OFF-state. I category: MSI CC The 540 is identical to the 541 but has inverting outputs. GENERAL DESCRIPTION The 74HC/HCT540 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V T = 25 C t = t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay A to Y C = 15 pF V = 5 V 9 11 ns PHL PLH n n L CC C input capacitance 3.5 3.5 pF I C power dissipation capacitance per buffer notes 1 and 2 39 44 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P = C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

Nexperia may also be referenced as

Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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