74HCT374D,652

74HC374 74HCT374 Octal D-type flip-flop positive edge-trigger 3-state Rev. 5 7 September 2021 Product data sheet 1. General description The 74HC374 74HCT374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC374: CMOS level For 74HCT374: TTL level Octal bus interface Non-inverting 3-state outputs 8-bit positive, edge-triggered register Common 3-state output enable input Independent register and 3-state buffer operation Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Latch-up performance exceeds 100 mA per JESD 78 Class II Level B ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC374D 40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74HCT374D 74HC374PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74HCT374PWNexperia 74HC374 74HCT374 Octal D-type flip-flop positive edge-trigger 3-state 4. Functional diagram 1 EN 11 C1 3 D0 Q0 2 11 4 D1 Q1 5 3 2 1D CP 7 Q2 6 D2 3 2 D0 Q0 4 5 Q3 8 D3 FF1 9 3-STATE 4 5 to D1 Q1 13 D4 Q4 12 OUTPUTS 7 6 FF8 7 6 D2 Q2 14 D5 Q5 15 8 9 8 9 D3 Q3 17 Q6 16 D6 13 12 13 12 D4 Q4 18 D7 Q7 19 14 15 14 15 D5 Q5 17 16 D6 Q6 CP 17 16 11 18 19 D7 Q7 1 OE 18 19 OE 1 mna891 mna196 mna892 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Functional diagram D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CP CP FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna893 Fig. 4. Logic diagram 74HC HCT374 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 7 September 2021 2 / 15