Product Information

74LV03D,118

74LV03D,118 electronic component of Nexperia

Datasheet
Logic Gates 3.3V QUAD 2-INPUT

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.7021 ea
Line Total: USD 0.7

2422 - Global Stock
Ships to you between
Mon. 27 May to Wed. 29 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
2218 - WHS 1


Ships to you between Mon. 27 May to Wed. 29 May

MOQ : 1
Multiples : 1

Stock Image

74LV03D,118
Nexperia

1 : USD 0.437
10 : USD 0.3507
100 : USD 0.2392
1000 : USD 0.1426
2500 : USD 0.1208
10000 : USD 0.115
25000 : USD 0.1138
50000 : USD 0.1127
100000 : USD 0.1092

     
Manufacturer
Product Category
Product
Logic Function
Logic Family
Number of Gates
Number of Input Lines
Number of Output Lines
High Level Output Current
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Hts Code
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74LV03 Quad 2-input NAND gate Rev. 4 31 August 2017 Product data sheet 1 General description The 74LV03 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT03. The 74LV03 provides the 2-input NAND function. The 74LV03 has open-drain N-transistor outputs, which are not clamped by a diode connected to V . In the OFF-state, i.e., when one input is LOW, the output may be CC pulled to any voltage between GND and V . This allows the device to be used as O(max) a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, these devices must have a pull-up resistor to establish a logic HIGH level. 2 Features and benefits Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical V (output ground bounce) < 0.8 V V = 3.3 V, T = 25 C OLP CC amb Typical V (output V undershoot) > 2 V V = 3.3 V, T = 25 C OHV OH CC amb Level shifter capability ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74LV03D -40 C to + 125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mmNexperia 74LV03 Quad 2-input NAND gate 4 Functional diagram 1 & 3 1 1A 2 1Y 3 2 1B 4 4 2A 6 & 2Y 6 5 5 2B Y 9 9 3A 8 3Y 8 & 10 3B 10 A 12 4A 12 4Y 11 11 13 4B & 13 B GND mna212 aaa-008083 001aab715 Figure 1.Logic symbol Figure 2.IEC logic symbol Figure 3.Logic diagram (one gate) 5 Pinning information 5.1 Pinning 74LV03 1A 1 14 V CC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 5 10 2B 3B 2Y 6 9 3A GND 7 8 3Y aaa-027324 Figure 4.Pin configuration SO14 5.2 Pin description Table 2.Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74LV03 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 4 31 August 2017 2 / 12

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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