74LV08D Nexperia

74LV08 Quad 2-input AND gate Rev. 03 6 April 2009 Product data sheet 1. General description The 74LV08 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The 74LV08 provides a quad 2-input AND function. 2. Features n Wide operating voltage: 1.0 V to 5.5 V n Optimized for low voltage applications: 1.0 V to 3.6 V n Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC n Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb n Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Multiple package options n Specied from - 40 Cto+85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV08N - 40 C to +125 C DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 74LV08D - 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LV08DB - 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads SOT337-1 body width 5.3 mm 74LV08PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm74LV08 NXP Semiconductors Quad 2-input AND gate 4. Functional diagram 1 & 3 2 1 1A 1Y 3 2 1B 4 & 6 4 2A 5 2Y 6 A 5 2B 9 3A Y 3Y 8 9 & 10 3B 8 B 10 mna221 12 4A 4Y 11 13 4B 12 & 11 mna222 13 mna223 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning 74LV08 74LV08 1 14 1A V CC 1B 2 13 4B 1A 1 14 V CC 1Y 3 12 4A 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2A 4 11 4Y 2B 5 10 3B 2B 5 10 3B 2Y 6 9 3A 6 9 2Y 3A GND 7 8 3Y GND 7 8 3Y 001aaj959 001aaj960 Fig 4. Pin conguration DIP14, SO14 Fig 5. Pin conguration (T)SSOP14 74LV08 3 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 6 April 2009 2 of 13