74LVC1G80GV-Q100,1

74LVC1G80-Q100 Single D-type flip-flop; positive-edge trigger Rev. 2 12 December 2016 Product data sheet 1. General description The 74LVC1G80-Q100 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 24 mA output drive (V =3.0 V) CC CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options74LVC1G80-Q100 Nexperia Single D-type flip-flop; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G80GW-Q100 40 C to +125 C TSSOP5 plastic thin shrink small outline package; SOT353-1 5 leads; body width 1.25 mm 74LVC1G80GV-Q100 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753 4. Marking Table 2. Marking codes [1] Type number Marking 74LVC1G80GW-Q100 VT 74LVC1G80GV-Q100 V80 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram '4  '    DFD  PQ Fig 1. Logic symbol Fig 2. IEC logic symbol & & & & ' 7* 7* 4 & & & & 7* 7* & & DPQ Fig 3. Logic diagram 74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 2 12 December 2016 2 of 15 &3 D &3 &3