Product Information

74LVC32APW,118

74LVC32APW,118 electronic component of Nexperia

Datasheet
IC: digital; OR; Ch: 4; IN: 2; CMOS,TTL; SMD; TSSOP14; LVC; -40÷125°C

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.3887 ea
Line Total: USD 0.39

5762 - Global Stock
Ships to you between
Thu. 16 May to Mon. 20 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
2425 - WHS 1


Ships to you between Fri. 10 May to Thu. 16 May

MOQ : 2500
Multiples : 2500

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74LVC32APW,118
Nexperia

2500 : USD 0.0968
7500 : USD 0.0968
12500 : USD 0.0968
25000 : USD 0.0968
50000 : USD 0.0968

7473 - WHS 2


Ships to you between
Fri. 17 May to Wed. 22 May

MOQ : 5
Multiples : 5

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74LVC32APW,118
Nexperia

5 : USD 0.2033
50 : USD 0.1616
150 : USD 0.1436
500 : USD 0.1213
2500 : USD 0.1114
5000 : USD 0.1055

5762 - WHS 3


Ships to you between Thu. 16 May to Mon. 20 May

MOQ : 1
Multiples : 1

Stock Image

74LVC32APW,118
Nexperia

1 : USD 0.3887
10 : USD 0.2829
100 : USD 0.1598
1000 : USD 0.1265
2500 : USD 0.1012
10000 : USD 0.0978
25000 : USD 0.092
50000 : USD 0.092
100000 : USD 0.0897

     
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Logic Function
Logic Family
Number of Gates
Number of Input Lines
Number of Output Lines
High Level Output Current
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
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74LVC32A Quad 2-input OR gate Rev. 8 27 August 2021 Product data sheet 1. General description The 74LVC32A is a quad 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power dissipation Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC32AD -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVC32APW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVC32ABQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LVC32A Quad 2-input OR gate 4. Functional diagram 1 1 3 2 4 1 6 1 1A 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B 1 8 10 9 3A 3Y 8 10 3B 12 12 4A 1 4Y 11 11 13 4B 13 mna242 mna243 Fig. 1. Logic symbol Fig. 2. IEC logic symbol A Y B mna241 Fig. 3. Logic diagram for one gate 5. Pinning information 5.1. Pinning 74LVC32A 74LVC32A 1 14 1A V CC 1B 2 13 4B 1A 1 14 V CC 3 12 1Y 4A 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2A 4 11 4Y 2B 5 10 3B 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y GND 7 8 3Y aaa-028965 aaa-028966 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 74LVC32A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 27 August 2021 2 / 13

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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